include/configs/walnut.h - platform/external/u-boot - Gitiles

 /*
  * (C) Copyright 2000-2005
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */

 /*
  * board/config.h - configuration options, board specific
  */

 #ifndef __CONFIG_H
 #define __CONFIG_H

 /*
  * High Level Configuration Options
  * (easy to change)
  */

 #define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
 #define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
 #define CONFIG_WALNUT		1	/* ...on a WALNUT board		*/
 					/* ...and on a SYCAMORE board	*/

 #define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/

 #define CONFIG_SYS_CLK_FREQ	33333333 /* external frequency to pll	*/

 #define CONFIG_PREBOOT	"echo;" \
 	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
 	"echo"

 #undef	CONFIG_BOOTARGS

 #define CONFIG_EXTRA_ENV_SETTINGS					\
 	"netdev=eth0\0"							\
 	"hostname=walnut\0"						\
 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
 		"nfsroot=${serverip}:${rootpath}\0"			\
 	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
 	"addip=setenv bootargs ${bootargs} "				\
 		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
 		":${hostname}:${netdev}:off panic=1\0"			\
 	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 	"flash_nfs=run nfsargs addip addtty;"				\
 		"bootm ${kernel_addr}\0"				\
 	"flash_self=run ramargs addip addtty;"				\
 		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
 	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"	\
 		"bootm\0"						\
 	"rootpath=/opt/eldk/ppc_4xx\0"					\
 	"bootfile=/tftpboot/walnut/uImage\0"				\
 	"kernel_addr=fff80000\0"					\
 	"ramdisk_addr=fff80000\0"					\
 	"initrd_high=30000000\0"					\
 	"load=tftp 100000 /tftpboot/walnut/u-boot.bin\0"		\
 	"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;"	\
 		"cp.b 100000 fffc0000 40000;"				\
 		"setenv filesize;saveenv\0"				\
 	"upd=run load;run update\0"					\
 	""
 #define CONFIG_BOOTCOMMAND	"run net_nfs"

 #if 0
 #define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
 #else
 #define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
 #endif

 #define CONFIG_BAUDRATE		115200

 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
 #define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		1	/* PHY address			*/

 #define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */

 #define CONFIG_NETCONSOLE		/* include NetConsole support	*/
 #define CONFIG_NET_MULTI		/* needed for NetConsole	*/

 #define CONFIG_RTC_DS174x	1	/* use DS1743 RTC in Walnut	*/


 /*
  * Command line configuration.
  */
 #include <config_cmd_default.h>

 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_DIAG
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_NFS
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_SNTP


 #undef CONFIG_WATCHDOG			/* watchdog disabled		*/

 #define CONFIG_SPD_EEPROM      1       /* use SPD EEPROM for setup    */

 /*
  * Miscellaneous configurable options
  */
 #define CFG_LONGHELP			/* undef to save memory		*/
 #define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
 #define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
 #define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 #define CFG_MAXARGS	16		/* max number of command args	*/
 #define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

 #define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
 #define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

 /*
  * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
  * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
  * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
  * The Linux BASE_BAUD define should match this configuration.
  *    baseBaud = cpuClock/(uartDivisor*16)
  * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
  * set Linux BASE_BAUD to 403200.
  */
 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
 #undef	CFG_EXT_SERIAL_CLOCK	       /* external serial clock */
 #undef	CFG_405_UART_ERRATA_59	       /* 405GP/CR Rev. D silicon */
 #define CFG_BASE_BAUD	    691200

 /* The following table includes the supported baudrates */
 #define CFG_BAUDRATE_TABLE  \
     {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}

 #define CFG_LOAD_ADDR		0x100000	/* default load address */
 #define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */

 #define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */

 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 #define CONFIG_LOOPW		1	/* enable loopw command		*/
 #define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 #define CONFIG_VERSION_VARIABLE 1	/* include version env variable */

 /*-----------------------------------------------------------------------
  * I2C stuff
  *-----------------------------------------------------------------------
  */
 #define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
 #define CFG_I2C_SLAVE		0x7F

 #define CFG_I2C_MULTI_EEPROMS
 #define CFG_I2C_EEPROM_ADDR	(0xa8>>1)
 #define CFG_I2C_EEPROM_ADDR_LEN 1
 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 #define CFG_EEPROM_PAGE_WRITE_BITS 3
 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10

 /*-----------------------------------------------------------------------
  * PCI stuff
  *-----------------------------------------------------------------------
  */
 #define PCI_HOST_ADAPTER 0		/* configure ar pci adapter	*/
 #define PCI_HOST_FORCE	1		/* configure as pci host	*/
 #define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/

 #define CONFIG_PCI			/* include pci support		*/
 #define CONFIG_PCI_HOST PCI_HOST_FORCE	/* select pci host function	*/
 #define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
 					/* resource configuration	*/
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup	*/

 #define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
 #define CFG_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */
 #define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
 #define CFG_PCI_PTM1MS	0x80000001	/* 2GB, enable hard-wired to 1	*/
 #define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
 #define CFG_PCI_PTM2LA	0x00000000	/* disabled			*/
 #define CFG_PCI_PTM2MS	0x00000000	/* disabled			*/
 #define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/

 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
  * Please note that CFG_SDRAM_BASE _must_ start at 0
  */
 #define CFG_SDRAM_BASE		0x00000000
 #define CFG_FLASH_BASE		0xFFF80000
 #define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
 #define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
 #define CFG_MONITOR_BASE	(-CFG_MONITOR_LEN)

 /*
  * Define here the location of the environment variables (FLASH or NVRAM).
  * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
  *	 supported for backward compatibility.
  */
 #if 1
 #define CFG_ENV_IS_IN_FLASH	1	/* use FLASH for environment vars	*/
 #else
 #define CFG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
 #endif

 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
 #define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

 /*-----------------------------------------------------------------------
  * FLASH organization
  */
 #define FLASH_BASE0_PRELIM	CFG_FLASH_BASE	/* FLASH bank #0		*/
 #define FLASH_BASE1_PRELIM	0		/* FLASH bank #1		*/

 #define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
 #define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/

 #define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
 #define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

 #define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */

 #define CFG_FLASH_ADDR0		0x5555
 #define CFG_FLASH_ADDR1		0x2aaa
 #define CFG_FLASH_WORD_SIZE	unsigned char

 #ifdef CFG_ENV_IS_IN_FLASH
 #define CFG_ENV_SECT_SIZE	0x10000		/* size of one complete sector	*/
 #define CFG_ENV_ADDR		(CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
 #define CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/

 /* Address and size of Redundant Environment Sector	*/
 #define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
 #define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
 #endif /* CFG_ENV_IS_IN_FLASH */

 /*-----------------------------------------------------------------------
  * NVRAM organization
  */
 #define CFG_NVRAM_BASE_ADDR	0xf0000000	/* NVRAM base address	*/
 #define CFG_NVRAM_SIZE		0x1ff8		/* NVRAM size	*/

 #ifdef CFG_ENV_IS_IN_NVRAM
 #define CFG_ENV_SIZE		0x1000		/* Size of Environment vars	*/
 #define CFG_ENV_ADDR		\
 	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)	/* Env	*/
 #endif

 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
 #define CFG_DCACHE_SIZE		16384	/* For AMCC 405 CPUs, older 405 ppc's	*/
 					/* have only 8kB, 16kB is save here	*/
 #define CFG_CACHELINE_SIZE	32	/* ...			*/
 #if defined(CONFIG_CMD_KGDB)
 #define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
 #endif

 /*-----------------------------------------------------------------------
  * External Bus Controller (EBC) Setup
  */

 /* Memory Bank 0 (Flash Bank 0) initialization					*/
 #define CFG_EBC_PB0AP		0x9B015480
 #define CFG_EBC_PB0CR		0xFFF18000  /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit	*/

 #define CFG_EBC_PB1AP		0x02815480
 #define CFG_EBC_PB1CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/

 #define CFG_EBC_PB2AP		0x04815A80
 #define CFG_EBC_PB2CR		0xF0118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit	*/

 #define CFG_EBC_PB3AP		0x01815280
 #define CFG_EBC_PB3CR		0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit	*/

 #define CFG_EBC_PB7AP		0x01815280
 #define CFG_EBC_PB7CR		0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit	*/

 /*-----------------------------------------------------------------------
  * External peripheral base address
  *-----------------------------------------------------------------------
  */
 #define CFG_KEY_REG_BASE_ADDR	0xF0100000
 #define CFG_IR_REG_BASE_ADDR	0xF0200000
 #define CFG_FPGA_REG_BASE_ADDR	0xF0300000

 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area
  */
 #define CFG_INIT_DCACHE_CS	4	/* use cs # 4 for data cache memory    */

 #define CFG_INIT_RAM_ADDR	0x40000000  /* inside of SDRAM			   */
 #define CFG_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
 #define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 #define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

 /*-----------------------------------------------------------------------
  * Definitions for Serial Presence Detect EEPROM address
  * (to get SDRAM settings)
  */
 #define SPD_EEPROM_ADDRESS	0x50

 /*
  * Internal Definitions
  *
  * Boot Flags
  */
 #define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
 #define BOOTFLAG_WARM	0x02		/* Software reboot			*/

 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
 #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
 #endif	/* __CONFIG_H */
	/*
	* (C) Copyright 2000-2005
	* Stefan Roese, DENX Software Engineering, sr@denx.de.
	*
	* See file CREDITS for list of people who contributed to this
	* project.
	*
	* This program is free software; you can redistribute it and/or
	* modify it under the terms of the GNU General Public License as
	* published by the Free Software Foundation; either version 2 of
	* the License, or (at your option) any later version.
	*
	* This program is distributed in the hope that it will be useful,
	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	* GNU General Public License for more details.
	*
	* You should have received a copy of the GNU General Public License
	* along with this program; if not, write to the Free Software
	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	* MA 02111-1307 USA
	*/

	/*
	* board/config.h - configuration options, board specific
	*/

	#ifndef __CONFIG_H
	#define __CONFIG_H

	/*
	* High Level Configuration Options
	* (easy to change)
	*/

	#define CONFIG_405GP 1 /* This is a PPC405 CPU */
	#define CONFIG_4xx 1 /* ...member of PPC4xx family */
	#define CONFIG_WALNUT 1 /* ...on a WALNUT board */
	/* ...and on a SYCAMORE board */

	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */

	#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */

	#define CONFIG_PREBOOT "echo;" \
	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
	"echo"

	#undef CONFIG_BOOTARGS

	#define CONFIG_EXTRA_ENV_SETTINGS \
	"netdev=eth0\0" \
	"hostname=walnut\0" \
	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	"nfsroot=${serverip}:${rootpath}\0" \
	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	"addip=setenv bootargs ${bootargs} " \
	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	":${hostname}:${netdev}:off panic=1\0" \
	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
	"flash_nfs=run nfsargs addip addtty;" \
	"bootm ${kernel_addr}\0" \
	"flash_self=run ramargs addip addtty;" \
	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
	"bootm\0" \
	"rootpath=/opt/eldk/ppc_4xx\0" \
	"bootfile=/tftpboot/walnut/uImage\0" \
	"kernel_addr=fff80000\0" \
	"ramdisk_addr=fff80000\0" \
	"initrd_high=30000000\0" \
	"load=tftp 100000 /tftpboot/walnut/u-boot.bin\0" \
	"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
	"cp.b 100000 fffc0000 40000;" \
	"setenv filesize;saveenv\0" \
	"upd=run load;run update\0" \
	""
	#define CONFIG_BOOTCOMMAND "run net_nfs"

	#if 0
	#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
	#else
	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	#endif

	#define CONFIG_BAUDRATE 115200

	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */

	#define CONFIG_MII 1 /* MII PHY management */
	#define CONFIG_PHY_ADDR 1 /* PHY address */

	#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */

	#define CONFIG_NETCONSOLE /* include NetConsole support */
	#define CONFIG_NET_MULTI /* needed for NetConsole */

	#define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Walnut */


	/*
	* Command line configuration.
	*/
	#include <config_cmd_default.h>

	#define CONFIG_CMD_ASKENV
	#define CONFIG_CMD_DATE
	#define CONFIG_CMD_DHCP
	#define CONFIG_CMD_DIAG
	#define CONFIG_CMD_EEPROM
	#define CONFIG_CMD_ELF
	#define CONFIG_CMD_I2C
	#define CONFIG_CMD_IRQ
	#define CONFIG_CMD_MII
	#define CONFIG_CMD_NET
	#define CONFIG_CMD_NFS
	#define CONFIG_CMD_PCI
	#define CONFIG_CMD_PING
	#define CONFIG_CMD_REGINFO
	#define CONFIG_CMD_SDRAM
	#define CONFIG_CMD_SNTP


	#undef CONFIG_WATCHDOG /* watchdog disabled */

	#define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */

	/*
	* Miscellaneous configurable options
	*/
	#define CFG_LONGHELP /* undef to save memory */
	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	#if defined(CONFIG_CMD_KGDB)
	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	#else
	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	#endif
	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	#define CFG_MAXARGS 16 /* max number of command args */
	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */

	#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
	#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */

	/*
	* If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
	* If CFG_405_UART_ERRATA_59, then UART divisor is 31.
	* Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
	* The Linux BASE_BAUD define should match this configuration.
	* baseBaud = cpuClock/(uartDivisor*16)
	* If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
	* set Linux BASE_BAUD to 403200.
	*/
	#undef CONFIG_SERIAL_SOFTWARE_FIFO
	#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
	#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
	#define CFG_BASE_BAUD 691200

	/* The following table includes the supported baudrates */
	#define CFG_BAUDRATE_TABLE \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}

	#define CFG_LOAD_ADDR 0x100000 /* default load address */
	#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */

	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */

	#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
	#define CONFIG_LOOPW 1 /* enable loopw command */
	#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
	#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */

	/*-----------------------------------------------------------------------
	* I2C stuff
	*-----------------------------------------------------------------------
	*/
	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
	#undef CONFIG_SOFT_I2C /* I2C bit-banged */
	#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
	#define CFG_I2C_SLAVE 0x7F

	#define CFG_I2C_MULTI_EEPROMS
	#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
	#define CFG_I2C_EEPROM_ADDR_LEN 1
	#define CFG_EEPROM_PAGE_WRITE_ENABLE
	#define CFG_EEPROM_PAGE_WRITE_BITS 3
	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10

	/*-----------------------------------------------------------------------
	* PCI stuff
	*-----------------------------------------------------------------------
	*/
	#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
	#define PCI_HOST_FORCE 1 /* configure as pci host */
	#define PCI_HOST_AUTO 2 /* detected via arbiter enable */

	#define CONFIG_PCI /* include pci support */
	#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
	#define CONFIG_PCI_PNP /* do pci plug-and-play */
	/* resource configuration */
	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */

	#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
	#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
	#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
	#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
	#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
	#define CFG_PCI_PTM2LA 0x00000000 /* disabled */
	#define CFG_PCI_PTM2MS 0x00000000 /* disabled */
	#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */

	/*-----------------------------------------------------------------------
	* Start addresses for the final memory configuration
	* (Set up by the startup code)
	* Please note that CFG_SDRAM_BASE _must_ start at 0
	*/
	#define CFG_SDRAM_BASE 0x00000000
	#define CFG_FLASH_BASE 0xFFF80000
	#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
	#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
	#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)

	/*
	* Define here the location of the environment variables (FLASH or NVRAM).
	* Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
	* supported for backward compatibility.
	*/
	#if 1
	#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
	#else
	#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
	#endif

	/*
	* For booting Linux, the board info and command line data
	* have to be in the first 8 MB of memory, since this is
	* the maximum mapped by the Linux kernel during initialization.
	*/
	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */

	/*-----------------------------------------------------------------------
	* FLASH organization
	*/
	#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
	#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */

	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
	#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */

	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */

	#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */

	#define CFG_FLASH_ADDR0 0x5555
	#define CFG_FLASH_ADDR1 0x2aaa
	#define CFG_FLASH_WORD_SIZE unsigned char

	#ifdef CFG_ENV_IS_IN_FLASH
	#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
	#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
	#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */

	/* Address and size of Redundant Environment Sector */
	#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
	#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
	#endif /* CFG_ENV_IS_IN_FLASH */

	/*-----------------------------------------------------------------------
	* NVRAM organization
	*/
	#define CFG_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */
	#define CFG_NVRAM_SIZE 0x1ff8 /* NVRAM size */

	#ifdef CFG_ENV_IS_IN_NVRAM
	#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */
	#define CFG_ENV_ADDR \
	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */
	#endif

	/*-----------------------------------------------------------------------
	* Cache Configuration
	*/
	#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
	/* have only 8kB, 16kB is save here */
	#define CFG_CACHELINE_SIZE 32 /* ... */
	#if defined(CONFIG_CMD_KGDB)
	#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
	#endif

	/*-----------------------------------------------------------------------
	* External Bus Controller (EBC) Setup
	*/

	/* Memory Bank 0 (Flash Bank 0) initialization */
	#define CFG_EBC_PB0AP 0x9B015480
	#define CFG_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */

	#define CFG_EBC_PB1AP 0x02815480
	#define CFG_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */

	#define CFG_EBC_PB2AP 0x04815A80
	#define CFG_EBC_PB2CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */

	#define CFG_EBC_PB3AP 0x01815280
	#define CFG_EBC_PB3CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */

	#define CFG_EBC_PB7AP 0x01815280
	#define CFG_EBC_PB7CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */

	/*-----------------------------------------------------------------------
	* External peripheral base address
	*-----------------------------------------------------------------------
	*/
	#define CFG_KEY_REG_BASE_ADDR 0xF0100000
	#define CFG_IR_REG_BASE_ADDR 0xF0200000
	#define CFG_FPGA_REG_BASE_ADDR 0xF0300000

	/*-----------------------------------------------------------------------
	* Definitions for initial stack pointer and data area
	*/
	#define CFG_INIT_DCACHE_CS 4 /* use cs # 4 for data cache memory */

	#define CFG_INIT_RAM_ADDR 0x40000000 /* inside of SDRAM */
	#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET

	/*-----------------------------------------------------------------------
	* Definitions for Serial Presence Detect EEPROM address
	* (to get SDRAM settings)
	*/
	#define SPD_EEPROM_ADDRESS 0x50

	/*
	* Internal Definitions
	*
	* Boot Flags
	*/
	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	#define BOOTFLAG_WARM 0x02 /* Software reboot */

	#if defined(CONFIG_CMD_KGDB)
	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
	#endif
	#endif /* __CONFIG_H */