arch/arm/dts/rk3568.dtsi - platform/external/u-boot - Gitiles

 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
  */

 #include "rk356x.dtsi"

 / {
 	compatible = "rockchip,rk3568";

 	sata0: sata@fc000000 {
 		compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
 		reg = <0 0xfc000000 0 0x1000>;
 		clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>,
 			 <&cru CLK_SATA0_RXOOB>;
 		clock-names = "sata", "pmalive", "rxoob";
 		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 		phys = <&combphy0 PHY_TYPE_SATA>;
 		phy-names = "sata-phy";
 		ports-implemented = <0x1>;
 		power-domains = <&power RK3568_PD_PIPE>;
 		status = "disabled";
 	};

 	pipe_phy_grf0: syscon@fdc70000 {
 		compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
 		reg = <0x0 0xfdc70000 0x0 0x1000>;
 	};

 	qos_pcie3x1: qos@fe190080 {
 		compatible = "rockchip,rk3568-qos", "syscon";
 		reg = <0x0 0xfe190080 0x0 0x20>;
 	};

 	qos_pcie3x2: qos@fe190100 {
 		compatible = "rockchip,rk3568-qos", "syscon";
 		reg = <0x0 0xfe190100 0x0 0x20>;
 	};

 	qos_sata0: qos@fe190200 {
 		compatible = "rockchip,rk3568-qos", "syscon";
 		reg = <0x0 0xfe190200 0x0 0x20>;
 	};

 	pcie30_phy_grf: syscon@fdcb8000 {
 		compatible = "rockchip,rk3568-pcie3-phy-grf", "syscon";
 		reg = <0x0 0xfdcb8000 0x0 0x10000>;
 	};

 	pcie30phy: phy@fe8c0000 {
 		compatible = "rockchip,rk3568-pcie3-phy";
 		reg = <0x0 0xfe8c0000 0x0 0x20000>;
 		#phy-cells = <0>;
 		clocks = <&pmucru CLK_PCIE30PHY_REF_M>, <&pmucru CLK_PCIE30PHY_REF_N>,
 			 <&cru PCLK_PCIE30PHY>;
 		clock-names = "refclk_m", "refclk_n", "pclk";
 		resets = <&cru SRST_PCIE30PHY>;
 		reset-names = "phy";
 		rockchip,phy-grf = <&pcie30_phy_grf>;
 		status = "disabled";
 	};

 	pcie3x1: pcie@fe270000 {
 		compatible = "rockchip,rk3568-pcie";
 		#address-cells = <3>;
 		#size-cells = <2>;
 		bus-range = <0x0 0xf>;
 		clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
 			 <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
 			 <&cru CLK_PCIE30X1_AUX_NDFT>;
 		clock-names = "aclk_mst", "aclk_slv",
 			      "aclk_dbi", "pclk", "aux";
 		device_type = "pci";
 		interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "sys", "pmc", "msg", "legacy", "err";
 		#interrupt-cells = <1>;
 		interrupt-map-mask = <0 0 0 7>;
 		interrupt-map = <0 0 0 1 &pcie3x1_intc 0>,
 				<0 0 0 2 &pcie3x1_intc 1>,
 				<0 0 0 3 &pcie3x1_intc 2>,
 				<0 0 0 4 &pcie3x1_intc 3>;
 		linux,pci-domain = <1>;
 		num-ib-windows = <6>;
 		num-ob-windows = <2>;
 		max-link-speed = <3>;
 		msi-map = <0x0 &gic 0x1000 0x1000>;
 		num-lanes = <1>;
 		phys = <&pcie30phy>;
 		phy-names = "pcie-phy";
 		power-domains = <&power RK3568_PD_PIPE>;
 		reg = <0x3 0xc0400000 0x0 0x00400000>,
 		      <0x0 0xfe270000 0x0 0x00010000>,
 		      <0x0 0xf2000000 0x0 0x00100000>;
 		ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>,
 			 <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x01e00000>,
 			 <0x03000000 0x0 0x40000000 0x3 0x40000000 0x0 0x40000000>;
 		reg-names = "dbi", "apb", "config";
 		resets = <&cru SRST_PCIE30X1_POWERUP>;
 		reset-names = "pipe";
 		/* bifurcation; lane1 when using 1+1 */
 		status = "disabled";

 		pcie3x1_intc: legacy-interrupt-controller {
 			interrupt-controller;
 			#address-cells = <0>;
 			#interrupt-cells = <1>;
 			interrupt-parent = <&gic>;
 			interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
 		};
 	};

 	pcie3x2: pcie@fe280000 {
 		compatible = "rockchip,rk3568-pcie";
 		#address-cells = <3>;
 		#size-cells = <2>;
 		bus-range = <0x0 0xf>;
 		clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
 			 <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
 			 <&cru CLK_PCIE30X2_AUX_NDFT>;
 		clock-names = "aclk_mst", "aclk_slv",
 			      "aclk_dbi", "pclk", "aux";
 		device_type = "pci";
 		interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "sys", "pmc", "msg", "legacy", "err";
 		#interrupt-cells = <1>;
 		interrupt-map-mask = <0 0 0 7>;
 		interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
 				<0 0 0 2 &pcie3x2_intc 1>,
 				<0 0 0 3 &pcie3x2_intc 2>,
 				<0 0 0 4 &pcie3x2_intc 3>;
 		linux,pci-domain = <2>;
 		num-ib-windows = <6>;
 		num-ob-windows = <2>;
 		max-link-speed = <3>;
 		msi-map = <0x0 &gic 0x2000 0x1000>;
 		num-lanes = <2>;
 		phys = <&pcie30phy>;
 		phy-names = "pcie-phy";
 		power-domains = <&power RK3568_PD_PIPE>;
 		reg = <0x3 0xc0800000 0x0 0x00400000>,
 		      <0x0 0xfe280000 0x0 0x00010000>,
 		      <0x0 0xf0000000 0x0 0x00100000>;
 		ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>,
 			 <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x01e00000>,
 			 <0x03000000 0x0 0x40000000 0x3 0x80000000 0x0 0x40000000>;
 		reg-names = "dbi", "apb", "config";
 		resets = <&cru SRST_PCIE30X2_POWERUP>;
 		reset-names = "pipe";
 		/* bifurcation; lane0 when using 1+1 */
 		status = "disabled";

 		pcie3x2_intc: legacy-interrupt-controller {
 			interrupt-controller;
 			#address-cells = <0>;
 			#interrupt-cells = <1>;
 			interrupt-parent = <&gic>;
 			interrupts = <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>;
 		};
 	};

 	gmac0: ethernet@fe2a0000 {
 		compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
 		reg = <0x0 0xfe2a0000 0x0 0x10000>;
 		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "macirq", "eth_wake_irq";
 		clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>,
 			 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>,
 			 <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>,
 			 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>;
 		clock-names = "stmmaceth", "mac_clk_rx",
 			      "mac_clk_tx", "clk_mac_refout",
 			      "aclk_mac", "pclk_mac",
 			      "clk_mac_speed", "ptp_ref";
 		resets = <&cru SRST_A_GMAC0>;
 		reset-names = "stmmaceth";
 		rockchip,grf = <&grf>;
 		snps,axi-config = <&gmac0_stmmac_axi_setup>;
 		snps,mixed-burst;
 		snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
 		snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
 		snps,tso;
 		status = "disabled";

 		mdio0: mdio {
 			compatible = "snps,dwmac-mdio";
 			#address-cells = <0x1>;
 			#size-cells = <0x0>;
 		};

 		gmac0_stmmac_axi_setup: stmmac-axi-config {
 			snps,blen = <0 0 0 0 16 8 4>;
 			snps,rd_osr_lmt = <8>;
 			snps,wr_osr_lmt = <4>;
 		};

 		gmac0_mtl_rx_setup: rx-queues-config {
 			snps,rx-queues-to-use = <1>;
 			queue0 {};
 		};

 		gmac0_mtl_tx_setup: tx-queues-config {
 			snps,tx-queues-to-use = <1>;
 			queue0 {};
 		};
 	};

 	combphy0: phy@fe820000 {
 		compatible = "rockchip,rk3568-naneng-combphy";
 		reg = <0x0 0xfe820000 0x0 0x100>;
 		clocks = <&pmucru CLK_PCIEPHY0_REF>,
 			 <&cru PCLK_PIPEPHY0>,
 			 <&cru PCLK_PIPE>;
 		clock-names = "ref", "apb", "pipe";
 		assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
 		assigned-clock-rates = <100000000>;
 		resets = <&cru SRST_PIPEPHY0>;
 		rockchip,pipe-grf = <&pipegrf>;
 		rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
 		#phy-cells = <1>;
 		status = "disabled";
 	};
 };

 &cpu0_opp_table {
 	opp-1992000000 {
 		opp-hz = /bits/ 64 <1992000000>;
 		opp-microvolt = <1150000 1150000 1150000>;
 	};
 };

 &pipegrf {
 	compatible = "rockchip,rk3568-pipe-grf", "syscon";
 };

 &power {
 	power-domain@RK3568_PD_PIPE {
 		reg = <RK3568_PD_PIPE>;
 		clocks = <&cru PCLK_PIPE>;
 		pm_qos = <&qos_pcie2x1>,
 			 <&qos_pcie3x1>,
 			 <&qos_pcie3x2>,
 			 <&qos_sata0>,
 			 <&qos_sata1>,
 			 <&qos_sata2>,
 			 <&qos_usb3_0>,
 			 <&qos_usb3_1>;
 		#power-domain-cells = <0>;
 	};
 };

 &usb_host0_xhci {
 	phys = <&usb2phy0_otg>, <&combphy0 PHY_TYPE_USB3>;
 	phy-names = "usb2-phy", "usb3-phy";
 };

 &vop {
 	compatible = "rockchip,rk3568-vop";
 };
	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	/*
	* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
	*/

	#include "rk356x.dtsi"

	/ {
	compatible = "rockchip,rk3568";

	sata0: sata@fc000000 {
	compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
	reg = <0 0xfc000000 0 0x1000>;
	clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>,
	<&cru CLK_SATA0_RXOOB>;
	clock-names = "sata", "pmalive", "rxoob";
	interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
	phys = <&combphy0 PHY_TYPE_SATA>;
	phy-names = "sata-phy";
	ports-implemented = <0x1>;
	power-domains = <&power RK3568_PD_PIPE>;
	status = "disabled";
	};

	pipe_phy_grf0: syscon@fdc70000 {
	compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
	reg = <0x0 0xfdc70000 0x0 0x1000>;
	};

	qos_pcie3x1: qos@fe190080 {
	compatible = "rockchip,rk3568-qos", "syscon";
	reg = <0x0 0xfe190080 0x0 0x20>;
	};

	qos_pcie3x2: qos@fe190100 {
	compatible = "rockchip,rk3568-qos", "syscon";
	reg = <0x0 0xfe190100 0x0 0x20>;
	};

	qos_sata0: qos@fe190200 {
	compatible = "rockchip,rk3568-qos", "syscon";
	reg = <0x0 0xfe190200 0x0 0x20>;
	};

	pcie30_phy_grf: syscon@fdcb8000 {
	compatible = "rockchip,rk3568-pcie3-phy-grf", "syscon";
	reg = <0x0 0xfdcb8000 0x0 0x10000>;
	};

	pcie30phy: phy@fe8c0000 {
	compatible = "rockchip,rk3568-pcie3-phy";
	reg = <0x0 0xfe8c0000 0x0 0x20000>;
	#phy-cells = <0>;
	clocks = <&pmucru CLK_PCIE30PHY_REF_M>, <&pmucru CLK_PCIE30PHY_REF_N>,
	<&cru PCLK_PCIE30PHY>;
	clock-names = "refclk_m", "refclk_n", "pclk";
	resets = <&cru SRST_PCIE30PHY>;
	reset-names = "phy";
	rockchip,phy-grf = <&pcie30_phy_grf>;
	status = "disabled";
	};

	pcie3x1: pcie@fe270000 {
	compatible = "rockchip,rk3568-pcie";
	#address-cells = <3>;
	#size-cells = <2>;
	bus-range = <0x0 0xf>;
	clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
	<&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
	<&cru CLK_PCIE30X1_AUX_NDFT>;
	clock-names = "aclk_mst", "aclk_slv",
	"aclk_dbi", "pclk", "aux";
	device_type = "pci";
	interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "sys", "pmc", "msg", "legacy", "err";
	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 7>;
	interrupt-map = <0 0 0 1 &pcie3x1_intc 0>,
	<0 0 0 2 &pcie3x1_intc 1>,
	<0 0 0 3 &pcie3x1_intc 2>,
	<0 0 0 4 &pcie3x1_intc 3>;
	linux,pci-domain = <1>;
	num-ib-windows = <6>;
	num-ob-windows = <2>;
	max-link-speed = <3>;
	msi-map = <0x0 &gic 0x1000 0x1000>;
	num-lanes = <1>;
	phys = <&pcie30phy>;
	phy-names = "pcie-phy";
	power-domains = <&power RK3568_PD_PIPE>;
	reg = <0x3 0xc0400000 0x0 0x00400000>,
	<0x0 0xfe270000 0x0 0x00010000>,
	<0x0 0xf2000000 0x0 0x00100000>;
	ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>,
	<0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x01e00000>,
	<0x03000000 0x0 0x40000000 0x3 0x40000000 0x0 0x40000000>;
	reg-names = "dbi", "apb", "config";
	resets = <&cru SRST_PCIE30X1_POWERUP>;
	reset-names = "pipe";
	/* bifurcation; lane1 when using 1+1 */
	status = "disabled";

	pcie3x1_intc: legacy-interrupt-controller {
	interrupt-controller;
	#address-cells = <0>;
	#interrupt-cells = <1>;
	interrupt-parent = <&gic>;
	interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
	};
	};

	pcie3x2: pcie@fe280000 {
	compatible = "rockchip,rk3568-pcie";
	#address-cells = <3>;
	#size-cells = <2>;
	bus-range = <0x0 0xf>;
	clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
	<&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
	<&cru CLK_PCIE30X2_AUX_NDFT>;
	clock-names = "aclk_mst", "aclk_slv",
	"aclk_dbi", "pclk", "aux";
	device_type = "pci";
	interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "sys", "pmc", "msg", "legacy", "err";
	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 7>;
	interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
	<0 0 0 2 &pcie3x2_intc 1>,
	<0 0 0 3 &pcie3x2_intc 2>,
	<0 0 0 4 &pcie3x2_intc 3>;
	linux,pci-domain = <2>;
	num-ib-windows = <6>;
	num-ob-windows = <2>;
	max-link-speed = <3>;
	msi-map = <0x0 &gic 0x2000 0x1000>;
	num-lanes = <2>;
	phys = <&pcie30phy>;
	phy-names = "pcie-phy";
	power-domains = <&power RK3568_PD_PIPE>;
	reg = <0x3 0xc0800000 0x0 0x00400000>,
	<0x0 0xfe280000 0x0 0x00010000>,
	<0x0 0xf0000000 0x0 0x00100000>;
	ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>,
	<0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x01e00000>,
	<0x03000000 0x0 0x40000000 0x3 0x80000000 0x0 0x40000000>;
	reg-names = "dbi", "apb", "config";
	resets = <&cru SRST_PCIE30X2_POWERUP>;
	reset-names = "pipe";
	/* bifurcation; lane0 when using 1+1 */
	status = "disabled";

	pcie3x2_intc: legacy-interrupt-controller {
	interrupt-controller;
	#address-cells = <0>;
	#interrupt-cells = <1>;
	interrupt-parent = <&gic>;
	interrupts = <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>;
	};
	};

	gmac0: ethernet@fe2a0000 {
	compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
	reg = <0x0 0xfe2a0000 0x0 0x10000>;
	interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "macirq", "eth_wake_irq";
	clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>,
	<&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>,
	<&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>,
	<&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>;
	clock-names = "stmmaceth", "mac_clk_rx",
	"mac_clk_tx", "clk_mac_refout",
	"aclk_mac", "pclk_mac",
	"clk_mac_speed", "ptp_ref";
	resets = <&cru SRST_A_GMAC0>;
	reset-names = "stmmaceth";
	rockchip,grf = <&grf>;
	snps,axi-config = <&gmac0_stmmac_axi_setup>;
	snps,mixed-burst;
	snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
	snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
	snps,tso;
	status = "disabled";

	mdio0: mdio {
	compatible = "snps,dwmac-mdio";
	#address-cells = <0x1>;
	#size-cells = <0x0>;
	};

	gmac0_stmmac_axi_setup: stmmac-axi-config {
	snps,blen = <0 0 0 0 16 8 4>;
	snps,rd_osr_lmt = <8>;
	snps,wr_osr_lmt = <4>;
	};

	gmac0_mtl_rx_setup: rx-queues-config {
	snps,rx-queues-to-use = <1>;
	queue0 {};
	};

	gmac0_mtl_tx_setup: tx-queues-config {
	snps,tx-queues-to-use = <1>;
	queue0 {};
	};
	};

	combphy0: phy@fe820000 {
	compatible = "rockchip,rk3568-naneng-combphy";
	reg = <0x0 0xfe820000 0x0 0x100>;
	clocks = <&pmucru CLK_PCIEPHY0_REF>,
	<&cru PCLK_PIPEPHY0>,
	<&cru PCLK_PIPE>;
	clock-names = "ref", "apb", "pipe";
	assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
	assigned-clock-rates = <100000000>;
	resets = <&cru SRST_PIPEPHY0>;
	rockchip,pipe-grf = <&pipegrf>;
	rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
	#phy-cells = <1>;
	status = "disabled";
	};
	};

	&cpu0_opp_table {
	opp-1992000000 {
	opp-hz = /bits/ 64 <1992000000>;
	opp-microvolt = <1150000 1150000 1150000>;
	};
	};

	&pipegrf {
	compatible = "rockchip,rk3568-pipe-grf", "syscon";
	};

	&power {
	power-domain@RK3568_PD_PIPE {
	reg = <RK3568_PD_PIPE>;
	clocks = <&cru PCLK_PIPE>;
	pm_qos = <&qos_pcie2x1>,
	<&qos_pcie3x1>,
	<&qos_pcie3x2>,
	<&qos_sata0>,
	<&qos_sata1>,
	<&qos_sata2>,
	<&qos_usb3_0>,
	<&qos_usb3_1>;
	#power-domain-cells = <0>;
	};
	};

	&usb_host0_xhci {
	phys = <&usb2phy0_otg>, <&combphy0 PHY_TYPE_USB3>;
	phy-names = "usb2-phy", "usb3-phy";
	};

	&vop {
	compatible = "rockchip,rk3568-vop";
	};