arch/arm/dts/s700.dtsi

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2017 Andreas Färber
 */

#include <dt-bindings/clock/actions,s700-cmu.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/actions,s700-reset.h>

/ {
	compatible = "actions,s700";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x0>;
			enable-method = "psci";
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x1>;
			enable-method = "psci";
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x2>;
			enable-method = "psci";
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x3>;
			enable-method = "psci";
		};
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		secmon@1f000000 {
			reg = <0x0 0x1f000000 0x0 0x1000000>;
			no-map;
		};
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	arm-pmu {
		compatible = "arm,cortex-a53-pmu";
		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
		             <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
		             <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
		             <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13
			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14
			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11
			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10
			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
	};

	hosc: hosc {
		compatible = "fixed-clock";
		clock-frequency = <24000000>;
		#clock-cells = <0>;
	};

	losc: losc {
		compatible = "fixed-clock";
		clock-frequency = <32768>;
		#clock-cells = <0>;
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		gic: interrupt-controller@e00f1000 {
			compatible = "arm,gic-400";
			reg = <0x0 0xe00f1000 0x0 0x1000>,
			      <0x0 0xe00f2000 0x0 0x2000>,
			      <0x0 0xe00f4000 0x0 0x2000>,
			      <0x0 0xe00f6000 0x0 0x2000>;
			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
			interrupt-controller;
			#interrupt-cells = <3>;
		};

		uart0: serial@e0120000 {
			compatible = "actions,s900-uart", "actions,owl-uart";
			reg = <0x0 0xe0120000 0x0 0x2000>;
			clocks = <&cmu CLK_UART0>;
			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		uart1: serial@e0122000 {
			compatible = "actions,s900-uart", "actions,owl-uart";
			reg = <0x0 0xe0122000 0x0 0x2000>;
			clocks = <&cmu CLK_UART1>;
			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		uart2: serial@e0124000 {
			compatible = "actions,s900-uart", "actions,owl-uart";
			reg = <0x0 0xe0124000 0x0 0x2000>;
			clocks = <&cmu CLK_UART2>;
			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		uart3: serial@e0126000 {
			compatible = "actions,s900-uart", "actions,owl-uart";
			reg = <0x0 0xe0126000 0x0 0x2000>;
			clocks = <&cmu CLK_UART3>;
			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		uart4: serial@e0128000 {
			compatible = "actions,s900-uart", "actions,owl-uart";
			reg = <0x0 0xe0128000 0x0 0x2000>;
			clocks = <&cmu CLK_UART4>;
			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		uart5: serial@e012a000 {
			compatible = "actions,s900-uart", "actions,owl-uart";
			reg = <0x0 0xe012a000 0x0 0x2000>;
			clocks = <&cmu CLK_UART5>;
			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		uart6: serial@e012c000 {
			compatible = "actions,s900-uart", "actions,owl-uart";
			reg = <0x0 0xe012c000 0x0 0x2000>;
			clocks = <&cmu CLK_UART6>;
			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		cmu: clock-controller@e0168000 {
			compatible = "actions,s700-cmu";
			reg = <0x0 0xe0168000 0x0 0x1000>;
			clocks = <&hosc>, <&losc>;
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		i2c0: i2c@e0170000 {
			compatible = "actions,s700-i2c";
			reg = <0 0xe0170000 0 0x1000>;
			clocks = <&cmu CLK_I2C0>;
			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c1: i2c@e0174000 {
			compatible = "actions,s700-i2c";
			reg = <0 0xe0174000 0 0x1000>;
			clocks = <&cmu CLK_I2C1>;
			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c2: i2c@e0178000 {
			compatible = "actions,s700-i2c";
			reg = <0 0xe0178000 0 0x1000>;
			clocks = <&cmu CLK_I2C2>;
			interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c3: i2c@e017c000 {
			compatible = "actions,s700-i2c";
			reg = <0 0xe017c000 0 0x1000>;
			clocks = <&cmu CLK_I2C3>;
			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		sps: power-controller@e01b0100 {
			compatible = "actions,s700-sps";
			reg = <0x0 0xe01b0100 0x0 0x100>;
			#power-domain-cells = <1>;
		};

		timer: timer@e024c000 {
			compatible = "actions,s700-timer";
			reg = <0x0 0xe024c000 0x0 0x4000>;
			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "timer1";
		};

		pinctrl: pinctrl@e01b0000 {
			compatible = "actions,s700-pinctrl";
			reg = <0x0 0xe01b0000 0x0 0x1000>;
			clocks = <&cmu CLK_GPIO>;
			gpio-controller;
			gpio-ranges = <&pinctrl 0 0 136>;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
		};
	};
};