| // SPDX-License-Identifier: GPL-2.0 |
| /* |
| * Copyright (C) 2021 PHYTEC America, LLC - https://www.phytec.com |
| * Author: Matt McKee <mmckee@phytec.com> |
| * |
| * Copyright (C) 2022 - 2024 PHYTEC Messtechnik GmbH |
| * Author: Wadim Egorov <w.egorov@phytec.de> |
| * |
| * Product homepage: |
| * https://www.phytec.com/product/phycore-am64x |
| */ |
| |
| #include "k3-am642-phycore-som-binman.dtsi" |
| |
| / { |
| chosen { |
| stdout-path = "serial2:115200n8"; |
| tick-timer = &main_timer0; |
| }; |
| |
| memory@80000000 { |
| bootph-all; |
| }; |
| }; |
| |
| &cbass_main { |
| bootph-all; |
| }; |
| |
| &dmsc { |
| bootph-all; |
| }; |
| |
| &dmss { |
| bootph-all; |
| }; |
| |
| &k3_clks { |
| bootph-all; |
| }; |
| |
| &k3_pds { |
| bootph-all; |
| }; |
| |
| &k3_reset { |
| bootph-all; |
| }; |
| |
| &main_bcdma { |
| bootph-all; |
| reg = <0x00 0x485c0100 0x00 0x100>, |
| <0x00 0x4c000000 0x00 0x20000>, |
| <0x00 0x4a820000 0x00 0x20000>, |
| <0x00 0x4aa40000 0x00 0x20000>, |
| <0x00 0x4bc00000 0x00 0x100000>, |
| <0x00 0x48600000 0x00 0x8000>, |
| <0x00 0x484a4000 0x00 0x2000>, |
| <0x00 0x484c2000 0x00 0x2000>; |
| reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt", |
| "cfg", "tchan", "rchan"; |
| }; |
| |
| &main_conf { |
| bootph-all; |
| chipid@14 { |
| bootph-all; |
| }; |
| }; |
| |
| &main_gpio0 { |
| bootph-all; |
| }; |
| |
| &main_mmc1_pins_default { |
| bootph-all; |
| }; |
| |
| &main_pktdma { |
| bootph-all; |
| reg = <0x00 0x485c0000 0x00 0x100>, |
| <0x00 0x4a800000 0x00 0x20000>, |
| <0x00 0x4aa00000 0x00 0x40000>, |
| <0x00 0x4b800000 0x00 0x400000>, |
| <0x00 0x485e0000 0x00 0x20000>, |
| <0x00 0x484a0000 0x00 0x4000>, |
| <0x00 0x484c0000 0x00 0x2000>, |
| <0x00 0x48430000 0x00 0x4000>; |
| reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt", "cfg", |
| "tchan", "rchan", "rflow"; |
| }; |
| |
| &main_pmx0 { |
| bootph-all; |
| }; |
| |
| &main_timer0 { |
| bootph-all; |
| clock-frequency = <200000000>; |
| }; |
| |
| &main_uart0 { |
| bootph-all; |
| }; |
| |
| &main_uart0_pins_default { |
| bootph-all; |
| }; |
| |
| &main_usb0_pins_default { |
| bootph-all; |
| }; |
| |
| &ospi0 { |
| bootph-all; |
| flash@0 { |
| bootph-all; |
| }; |
| }; |
| |
| &ospi0_pins_default { |
| bootph-all; |
| }; |
| |
| &sdhci0 { |
| bootph-all; |
| }; |
| |
| &sdhci1 { |
| bootph-all; |
| }; |
| |
| &secure_proxy_main { |
| bootph-all; |
| }; |
| |
| &usbss0 { |
| bootph-all; |
| }; |
| |
| &usb0 { |
| bootph-all; |
| }; |