Coding style cleanup
diff --git a/board/sandburst/common/sb_common.c b/board/sandburst/common/sb_common.c
index 1251bc9..3530416 100644
--- a/board/sandburst/common/sb_common.c
+++ b/board/sandburst/common/sb_common.c
@@ -34,7 +34,7 @@
/*************************************************************************
* metrobox_get_master
*
- * PRI_N - active low signal. If the GPIO pin is low we are the master
+ * PRI_N - active low signal. If the GPIO pin is low we are the master
*
************************************************************************/
int sbcommon_get_master(void)
@@ -81,7 +81,7 @@
unsigned short sernum;
/* Get the board serial number from eeprom */
- /* Initialize I2C */
+ /* Initialize I2C */
i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
/* Read 256 bytes in EEPROM */
@@ -96,7 +96,7 @@
/*************************************************************************
* sbcommon_fans
*
- * Spin up fans 2 & 3 to get some air moving. OS will take care
+ * Spin up fans 2 & 3 to get some air moving. OS will take care
* of the rest. This is mostly a precaution...
*
* Assumes i2c bus 1 is ready.
@@ -253,8 +253,8 @@
/*************************************************************************
* fixed sdram init -- doesn't use serial presence detect.
*
- * Assumes: 128 MB, non-ECC, non-registered
- * PLB @ 133 MHz
+ * Assumes: 128 MB, non-ECC, non-registered
+ * PLB @ 133 MHz
*
************************************************************************/
long int fixed_sdram (void)
@@ -264,11 +264,11 @@
/*--------------------------------------------------------------------
* Setup some default
*------------------------------------------------------------------*/
- mtsdram (mem_uabba, 0x00000000); /* ubba=0 (default) */
- mtsdram (mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
- mtsdram (mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
- mtsdram (mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */
- mtsdram (mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
+ mtsdram (mem_uabba, 0x00000000); /* ubba=0 (default) */
+ mtsdram (mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
+ mtsdram (mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
+ mtsdram (mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */
+ mtsdram (mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
/*--------------------------------------------------------------------
* Setup for board-specific specific mem
@@ -276,25 +276,25 @@
/*
* Following for CAS Latency = 2.5 @ 133 MHz PLB
*/
- mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
- mtsdram (mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
- /* RA=10 RD=3 */
+ mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
+ mtsdram (mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
+ /* RA=10 RD=3 */
mtsdram (mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
- mtsdram (mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
- mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
- udelay (400); /* Delay 200 usecs (min) */
+ mtsdram (mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
+ mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
+ udelay (400); /* Delay 200 usecs (min) */
/*--------------------------------------------------------------------
* Enable the controller, then wait for DCEN to complete
*------------------------------------------------------------------*/
- mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
+ mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
for (;;) {
mfsdram (mem_mcsts, reg);
if (reg & 0x80000000)
break;
}
- return (128 * 1024 * 1024); /* 128 MB */
+ return (128 * 1024 * 1024); /* 128 MB */
}
#endif /* !defined(CONFIG_SPD_EEPROM) */