| if ARCH_STM32MP |
| |
| config SPL |
| select SPL_BOARD_INIT |
| select SPL_CLK |
| select SPL_DM |
| select SPL_DM_SEQ_ALIAS |
| select SPL_DRIVERS_MISC_SUPPORT |
| select SPL_FRAMEWORK |
| select SPL_GPIO_SUPPORT |
| select SPL_LIBCOMMON_SUPPORT |
| select SPL_LIBGENERIC_SUPPORT |
| select SPL_OF_CONTROL |
| select SPL_OF_TRANSLATE |
| select SPL_PINCTRL |
| select SPL_REGMAP |
| select SPL_DM_RESET |
| select SPL_SERIAL_SUPPORT |
| select SPL_SYSCON |
| select SPL_WATCHDOG_SUPPORT |
| imply BOOTSTAGE_STASH if SPL_BOOTSTAGE |
| imply SPL_BOOTSTAGE if BOOTSTAGE |
| imply SPL_DISPLAY_PRINT |
| imply SPL_LIBDISK_SUPPORT |
| |
| config SYS_SOC |
| default "stm32mp" |
| |
| config SYS_MALLOC_LEN |
| default 0x2000000 |
| |
| config ENV_SIZE |
| default 0x2000 |
| |
| config TARGET_STM32MP1 |
| bool "Support stm32mp1xx" |
| select ARCH_SUPPORT_PSCI if !STM32MP1_TRUSTED |
| select CPU_V7A |
| select CPU_V7_HAS_NONSEC if !STM32MP1_TRUSTED |
| select CPU_V7_HAS_VIRT |
| select OF_BOARD_SETUP |
| select PINCTRL_STM32 |
| select STM32_RCC |
| select STM32_RESET |
| select SYS_ARCH_TIMER |
| imply BOOTCOUNT_LIMIT |
| imply BOOTSTAGE |
| imply CMD_BOOTCOUNT |
| imply CMD_BOOTSTAGE |
| imply SYSRESET_PSCI if STM32MP1_TRUSTED |
| imply SYSRESET_SYSCON if !STM32MP1_TRUSTED |
| help |
| target STMicroelectronics SOC STM32MP1 family |
| STM32MP157, STM32MP153 or STM32MP151 |
| STMicroelectronics MPU with core ARMv7 |
| dual core A7 for STM32MP157/3, monocore for STM32MP151 |
| |
| config STM32MP1_TRUSTED |
| bool "Support trusted boot with TF-A" |
| default y if !SPL |
| select ARM_SMCCC |
| help |
| Say Y here to enable boot with TF-A |
| Trusted boot chain is : |
| BootRom => TF-A.stm32 (clock & DDR) => U-Boot.stm32 |
| TF-A monitor provides proprietary SMC to manage secure devices |
| |
| config STM32MP1_OPTEE |
| bool "Support trusted boot with TF-A and OP-TEE" |
| depends on STM32MP1_TRUSTED |
| default n |
| help |
| Say Y here to enable boot with TF-A and OP-TEE |
| Trusted boot chain is : |
| BootRom => TF-A.stm32 (clock & DDR) => OP-TEE => U-Boot.stm32 |
| OP-TEE monitor provides ST SMC to access to secure resources |
| |
| config SYS_TEXT_BASE |
| prompt "U-Boot base address" |
| default 0xC0100000 |
| help |
| configure the U-Boot base address |
| when DDR driver is used: |
| DDR + 1MB (0xC0100000) |
| |
| config NR_DRAM_BANKS |
| default 1 |
| |
| config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2 |
| hex "Partition on MMC2 to use to load U-Boot from" |
| depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION |
| default 1 |
| help |
| Partition on the second MMC to load U-Boot from when the MMC is being |
| used in raw mode |
| |
| config STM32_ETZPC |
| bool "STM32 Extended TrustZone Protection" |
| depends on TARGET_STM32MP1 |
| default y |
| help |
| Say y to enable STM32 Extended TrustZone Protection |
| |
| config CMD_STM32KEY |
| bool "command stm32key to fuse public key hash" |
| default y |
| depends on CMD_FUSE |
| help |
| fuse public key hash in corresponding fuse used to authenticate |
| binary. |
| |
| config BOOTSTAGE_STASH_ADDR |
| default 0xC3000000 |
| |
| if BOOTCOUNT_LIMIT |
| config SYS_BOOTCOUNT_SINGLEWORD |
| default y |
| |
| # TAMP_BOOTCOUNT = TAMP_BACKUP_REGISTER(21) |
| config SYS_BOOTCOUNT_ADDR |
| default 0x5C00A154 |
| endif |
| |
| if DEBUG_UART |
| |
| config DEBUG_UART_BOARD_INIT |
| default y |
| |
| # debug on UART4 by default |
| config DEBUG_UART_BASE |
| default 0x40010000 |
| |
| # clock source is HSI on reset |
| config DEBUG_UART_CLOCK |
| default 64000000 |
| endif |
| |
| source "board/st/stm32mp1/Kconfig" |
| |
| endif |