* Patches by Xianghua Xiao, 15 Oct 2003:
- Added Motorola CPU 8540/8560 support (cpu/85xx)
- Added Motorola MPC8540ADS board support (board/mpc8540ads)
- Added Motorola MPC8560ADS board support (board/mpc8560ads)
* Minor code cleanup
diff --git a/board/adderII/adderII.h b/board/adderII/adderII.h
index 24e2d93..cf2e673 100644
--- a/board/adderII/adderII.h
+++ b/board/adderII/adderII.h
@@ -41,5 +41,3 @@
* | |
* | ... |
*****************************************************************************/
-
-
diff --git a/board/adderII/config.mk b/board/adderII/config.mk
index c23d942..27b3c41 100644
--- a/board/adderII/config.mk
+++ b/board/adderII/config.mk
@@ -26,4 +26,3 @@
#
TEXT_BASE = 0xFE000000
-
diff --git a/board/adderII/u-boot.lds b/board/adderII/u-boot.lds
index 666e843..cb4d385 100644
--- a/board/adderII/u-boot.lds
+++ b/board/adderII/u-boot.lds
@@ -144,4 +144,3 @@
_end = . ;
PROVIDE (end = .);
}
-
diff --git a/board/dave/PPChameleonEVB/PPChameleonEVB.c b/board/dave/PPChameleonEVB/PPChameleonEVB.c
index 811f6f8..803c798 100644
--- a/board/dave/PPChameleonEVB/PPChameleonEVB.c
+++ b/board/dave/PPChameleonEVB/PPChameleonEVB.c
@@ -51,7 +51,7 @@
int board_pre_init (void)
{
out32(GPIO0_OR, CFG_NAND0_CE); /* set initial outputs */
- out32(GPIO0_OR, CFG_NAND1_CE); /* set initial outputs */
+ out32(GPIO0_OR, CFG_NAND1_CE); /* set initial outputs */
/*
* IRQ 0-15 405GP internally generated; active high; level sensitive
diff --git a/board/dave/PPChameleonEVB/flash.c b/board/dave/PPChameleonEVB/flash.c
index 110e021..d57c58d 100644
--- a/board/dave/PPChameleonEVB/flash.c
+++ b/board/dave/PPChameleonEVB/flash.c
@@ -46,8 +46,8 @@
#else
unsigned long size_b0;
int i;
- uint pbcr;
- unsigned long base_b0;
+ uint pbcr;
+ unsigned long base_b0;
int size_val = 0;
/* Init: no FLASHes known */
@@ -64,14 +64,14 @@
size_b0, size_b0<<20);
}
- /* Setup offsets */
- flash_get_offsets (-size_b0, &flash_info[0]);
+ /* Setup offsets */
+ flash_get_offsets (-size_b0, &flash_info[0]);
- /* Re-do sizing to get full correct info */
- mtdcr(ebccfga, pb0cr);
- pbcr = mfdcr(ebccfgd);
- mtdcr(ebccfga, pb0cr);
- base_b0 = -size_b0;
+ /* Re-do sizing to get full correct info */
+ mtdcr(ebccfga, pb0cr);
+ pbcr = mfdcr(ebccfgd);
+ mtdcr(ebccfga, pb0cr);
+ base_b0 = -size_b0;
switch (size_b0) {
case 1 << 20:
size_val = 0;
@@ -90,15 +90,15 @@
break;
}
pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
- mtdcr(ebccfgd, pbcr);
+ mtdcr(ebccfgd, pbcr);
- /* Monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
- -CFG_MONITOR_LEN,
- 0xffffffff,
- &flash_info[0]);
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ -CFG_MONITOR_LEN,
+ 0xffffffff,
+ &flash_info[0]);
- flash_info[0].size = size_b0;
+ flash_info[0].size = size_b0;
return (size_b0);
#endif
diff --git a/board/dave/common/flash.c b/board/dave/common/flash.c
index 3cdbaa9..feea093 100644
--- a/board/dave/common/flash.c
+++ b/board/dave/common/flash.c
@@ -40,11 +40,11 @@
short n;
/* set up sector start address table */
- if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+ if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) {
for (i = 0; i < info->sector_count; i++)
info->start[i] = base + (i * 0x00010000);
- } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
+ } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) {
@@ -58,7 +58,7 @@
base += 64 << 10;
++i;
}
- } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
+ } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) {
@@ -75,7 +75,7 @@
--i;
info->start[i] = base;
}
- } else {
+ } else {
if (info->flash_id & FLASH_BTYPE) {
/* set sector offsets for bottom boot block type */
info->start[0] = base + 0x00000000;
@@ -103,10 +103,10 @@
void flash_print_info (flash_info_t *info)
{
int i;
- int k;
- int size;
- int erased;
- volatile unsigned long *flash;
+ int k;
+ int size;
+ int erased;
+ volatile unsigned long *flash;
if (info->flash_id == FLASH_UNKNOWN) {
printf ("missing or unknown FLASH type\n");
@@ -164,28 +164,28 @@
printf (" Sector Start Addresses:");
for (i=0; i<info->sector_count; ++i) {
#ifdef CFG_FLASH_EMPTY_INFO
- /*
- * Check if whole sector is erased
- */
- if (i != (info->sector_count-1))
- size = info->start[i+1] - info->start[i];
- else
- size = info->start[0] + info->size - info->start[i];
- erased = 1;
- flash = (volatile unsigned long *)info->start[i];
- size = size >> 2; /* divide by 4 for longword access */
- for (k=0; k<size; k++)
- {
- if (*flash++ != 0xffffffff)
- {
- erased = 0;
- break;
- }
- }
+ /*
+ * Check if whole sector is erased
+ */
+ if (i != (info->sector_count-1))
+ size = info->start[i+1] - info->start[i];
+ else
+ size = info->start[0] + info->size - info->start[i];
+ erased = 1;
+ flash = (volatile unsigned long *)info->start[i];
+ size = size >> 2; /* divide by 4 for longword access */
+ for (k=0; k<size; k++)
+ {
+ if (*flash++ != 0xffffffff)
+ {
+ erased = 0;
+ break;
+ }
+ }
if ((i % 5) == 0)
printf ("\n ");
- /* print empty and read-only info */
+ /* print empty and read-only info */
printf (" %08lX%s%s",
info->start[i],
erased ? " E" : " ",
@@ -219,7 +219,7 @@
short n;
CFG_FLASH_WORD_SIZE value;
ulong base = (ulong)addr;
- volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)addr;
+ volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)addr;
/* Write auto select command: read Manufacturer ID */
addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
@@ -288,42 +288,42 @@
break; /* => 2 MB */
case (CFG_FLASH_WORD_SIZE)STM_ID_29W320DT:
- info->flash_id += FLASH_STMW320DT;
- info->sector_count = 67;
+ info->flash_id += FLASH_STMW320DT;
+ info->sector_count = 67;
info->size = 0x00400000; break; /* => 4 MB */
case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T:
- info->flash_id += FLASH_AM320T;
- info->sector_count = 71;
+ info->flash_id += FLASH_AM320T;
+ info->sector_count = 71;
info->size = 0x00400000; break; /* => 4 MB */
case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B:
- info->flash_id += FLASH_AM320B;
+ info->flash_id += FLASH_AM320B;
info->sector_count = 71;
info->size = 0x00400000; break; /* => 4 MB */
case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322T:
- info->flash_id += FLASH_AMDL322T;
- info->sector_count = 71;
+ info->flash_id += FLASH_AMDL322T;
+ info->sector_count = 71;
info->size = 0x00400000; break; /* => 4 MB */
case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322B:
- info->flash_id += FLASH_AMDL322B;
+ info->flash_id += FLASH_AMDL322B;
info->sector_count = 71;
info->size = 0x00400000; break; /* => 4 MB */
case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323T:
- info->flash_id += FLASH_AMDL323T;
+ info->flash_id += FLASH_AMDL323T;
info->sector_count = 71;
info->size = 0x00400000; break; /* => 4 MB */
case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323B:
- info->flash_id += FLASH_AMDL323B;
+ info->flash_id += FLASH_AMDL323B;
info->sector_count = 71;
info->size = 0x00400000; break; /* => 4 MB */
case (CFG_FLASH_WORD_SIZE)AMD_ID_LV640U:
- info->flash_id += FLASH_AM640U;
+ info->flash_id += FLASH_AM640U;
info->sector_count = 128;
info->size = 0x00800000; break; /* => 8 MB */
@@ -346,11 +346,11 @@
}
/* set up sector start address table */
- if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+ if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) {
for (i = 0; i < info->sector_count; i++)
info->start[i] = base + (i * 0x00010000);
- } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
+ } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) {
@@ -364,7 +364,7 @@
base += 64 << 10;
++i;
}
- } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
+ } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) {
@@ -381,13 +381,13 @@
--i;
info->start[i] = base;
}
- } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) {
+ } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) {
/* set sector offsets for top boot block type */
base += info->size;
i = info->sector_count;
- /* 1 x 16k boot sector */
+ /* 1 x 16k boot sector */
base -= 16 << 10;
- --i;
+ --i;
info->start[i] = base;
/* 2 x 8k boot sectors */
for (n=0; n<2; ++n) {
@@ -395,9 +395,9 @@
--i;
info->start[i] = base;
}
- /* 1 x 32k boot sector */
+ /* 1 x 32k boot sector */
base -= 32 << 10;
- --i;
+ --i;
info->start[i] = base;
while (i > 0) { /* 64k regular sectors */
@@ -405,7 +405,7 @@
--i;
info->start[i] = base;
}
- } else {
+ } else {
if (info->flash_id & FLASH_BTYPE) {
/* set sector offsets for bottom boot block type */
info->start[0] = base + 0x00000000;
@@ -432,10 +432,10 @@
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
/* D0 = 1 if protected */
addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
- info->protect[i] = 0;
- else
- info->protect[i] = addr2[CFG_FLASH_READ2] & 1;
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+ info->protect[i] = 0;
+ else
+ info->protect[i] = addr2[CFG_FLASH_READ2] & 1;
}
/*
@@ -459,7 +459,7 @@
volatile CFG_FLASH_WORD_SIZE *addr2;
int flag, prot, sect, l_sect;
ulong start, now, last;
- int i;
+ int i;
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
@@ -498,25 +498,25 @@
for (sect = s_first; sect<=s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[sect]);
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
- addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
- addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
- addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080;
- addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
- addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
- addr2[0] = (CFG_FLASH_WORD_SIZE)0x00500050; /* block erase */
- for (i=0; i<50; i++)
- udelay(1000); /* wait 1 ms */
- } else {
- if (sect == s_first) {
- addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
- addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
- addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080;
- addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
- addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
- }
- addr2[0] = (CFG_FLASH_WORD_SIZE)0x00300030; /* sector erase */
- }
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
+ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080;
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
+ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+ addr2[0] = (CFG_FLASH_WORD_SIZE)0x00500050; /* block erase */
+ for (i=0; i<50; i++)
+ udelay(1000); /* wait 1 ms */
+ } else {
+ if (sect == s_first) {
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
+ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080;
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
+ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+ }
+ addr2[0] = (CFG_FLASH_WORD_SIZE)0x00300030; /* sector erase */
+ }
l_sect = sect;
}
}
@@ -637,42 +637,42 @@
*/
static int write_word (flash_info_t *info, ulong dest, ulong data)
{
- volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[0]);
- volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *)dest;
- volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *)&data;
+ volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[0]);
+ volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *)dest;
+ volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *)&data;
ulong start;
int flag;
- int i;
+ int i;
/* Check if Flash is (sufficiently) erased */
if ((*((volatile CFG_FLASH_WORD_SIZE *)dest) &
- (CFG_FLASH_WORD_SIZE)data) != (CFG_FLASH_WORD_SIZE)data) {
+ (CFG_FLASH_WORD_SIZE)data) != (CFG_FLASH_WORD_SIZE)data) {
return (2);
}
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
- for (i=0; i<4/sizeof(CFG_FLASH_WORD_SIZE); i++)
- {
- addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
- addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
- addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00A000A0;
+ for (i=0; i<4/sizeof(CFG_FLASH_WORD_SIZE); i++)
+ {
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
+ addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00A000A0;
- dest2[i] = data2[i];
+ dest2[i] = data2[i];
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
- /* data polling for D7 */
- start = get_timer (0);
- while ((dest2[i] & (CFG_FLASH_WORD_SIZE)0x00800080) !=
- (data2[i] & (CFG_FLASH_WORD_SIZE)0x00800080)) {
- if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- }
+ /* data polling for D7 */
+ start = get_timer (0);
+ while ((dest2[i] & (CFG_FLASH_WORD_SIZE)0x00800080) !=
+ (data2[i] & (CFG_FLASH_WORD_SIZE)0x00800080)) {
+ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ return (1);
+ }
+ }
+ }
return (0);
}
diff --git a/board/dave/common/fpga.c b/board/dave/common/fpga.c
index 9547325..5b5b5e9 100644
--- a/board/dave/common/fpga.c
+++ b/board/dave/common/fpga.c
@@ -57,16 +57,16 @@
#define SET_FPGA(data) out32(GPIO0_OR, data)
#define FPGA_WRITE_1 { \
- SET_FPGA(FPGA_PRG | FPGA_DATA); /* set clock to 0 */ \
- SET_FPGA(FPGA_PRG | FPGA_DATA); /* set data to 1 */ \
- SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); /* set clock to 1 */ \
- SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */
+ SET_FPGA(FPGA_PRG | FPGA_DATA); /* set clock to 0 */ \
+ SET_FPGA(FPGA_PRG | FPGA_DATA); /* set data to 1 */ \
+ SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); /* set clock to 1 */ \
+ SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */
#define FPGA_WRITE_0 { \
- SET_FPGA(FPGA_PRG | FPGA_DATA); /* set clock to 0 */ \
- SET_FPGA(FPGA_PRG); /* set data to 0 */ \
- SET_FPGA(FPGA_PRG | FPGA_CLK); /* set clock to 1 */ \
- SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */
+ SET_FPGA(FPGA_PRG | FPGA_DATA); /* set clock to 0 */ \
+ SET_FPGA(FPGA_PRG); /* set data to 0 */ \
+ SET_FPGA(FPGA_PRG | FPGA_CLK); /* set clock to 1 */ \
+ SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */
#if 0
static int fpga_boot (unsigned char *fpgadata, int size)
diff --git a/board/dbau1x00/memsetup.S b/board/dbau1x00/memsetup.S
index 34ba2da..6c61e6f 100644
--- a/board/dbau1x00/memsetup.S
+++ b/board/dbau1x00/memsetup.S
@@ -9,17 +9,17 @@
memsetup:
/* First setup pll:s to make serial work ok */
/* We have a 12 MHz crystal */
- li t0, SYS_CPUPLL
- li t1, 0x21 /* 396 MHz */
- sw t1, 0(t0)
- sync
- nop
+ li t0, SYS_CPUPLL
+ li t1, 0x21 /* 396 MHz */
+ sw t1, 0(t0)
+ sync
+ nop
- /* Setup AUX PLL */
+ /* Setup AUX PLL */
li t0, SYS_AUXPLL
li t1, 8 /* 96 MHz */
- sw t1, 0(t0) /* aux pll */
- sync
+ sw t1, 0(t0) /* aux pll */
+ sync
/* SDCS 0,1 SDRAM */
li t0, MEM_SDMODE0
diff --git a/board/dk1c20/config.mk b/board/dk1c20/config.mk
index 12c74e6..d200715 100644
--- a/board/dk1c20/config.mk
+++ b/board/dk1c20/config.mk
@@ -27,4 +27,3 @@
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG
endif
-
diff --git a/board/dk1c20/u-boot.lds b/board/dk1c20/u-boot.lds
index beedd54..a7d35af 100644
--- a/board/dk1c20/u-boot.lds
+++ b/board/dk1c20/u-boot.lds
@@ -33,17 +33,17 @@
cpu/nios/start.o (.text)
*(.text)
}
- __text_end = .;
+ __text_end = .;
- . = ALIGN(4);
- .rodata :
+ . = ALIGN(4);
+ .rodata :
{
*(.rodata)
}
__rodata_end = .;
- . = ALIGN(4);
- .data :
+ . = ALIGN(4);
+ .data :
{
*(.data)
}
@@ -59,12 +59,11 @@
__u_boot_cmd_end = .;
__bss_start = .;
- . = ALIGN(4);
- .bss :
+ . = ALIGN(4);
+ .bss :
{
*(.bss)
}
. = ALIGN(4);
__bss_end = .;
}
-
diff --git a/board/dk1c20/vectors.S b/board/dk1c20/vectors.S
index e2baaf5..7094eb6 100644
--- a/board/dk1c20/vectors.S
+++ b/board/dk1c20/vectors.S
@@ -120,5 +120,3 @@
.long _def_xhandler@h /* Vector 61 */
.long _def_xhandler@h /* Vector 62 */
.long _def_xhandler@h /* Vector 63 */
-
-
diff --git a/board/esd/common/xilinx_jtag/lenval.c b/board/esd/common/xilinx_jtag/lenval.c
index a18a16e..7316266 100644
--- a/board/esd/common/xilinx_jtag/lenval.c
+++ b/board/esd/common/xilinx_jtag/lenval.c
@@ -64,7 +64,7 @@
* Returns: void.
*****************************************************************************/
void initLenVal( lenVal* plv,
- long lValue )
+ long lValue )
{
plv->len = 1;
plv->val[0] = (unsigned char)lValue;
@@ -79,8 +79,8 @@
* Returns: short - 0 = mismatch; 1 = equal.
*****************************************************************************/
short EqualLenVal( lenVal* plvTdoExpected,
- lenVal* plvTdoCaptured,
- lenVal* plvTdoMask )
+ lenVal* plvTdoCaptured,
+ lenVal* plvTdoMask )
{
short sEqual;
short sIndex;
@@ -120,8 +120,8 @@
* Returns: short - the bit value.
*****************************************************************************/
short RetBit( lenVal* plv,
- int iByte,
- int iBit )
+ int iByte,
+ int iBit )
{
/* assert( ( iByte >= 0 ) && ( iByte < plv->len ) ); */
/* assert( ( iBit >= 0 ) && ( iBit < 8 ) ); */
@@ -139,9 +139,9 @@
* Returns: void.
*****************************************************************************/
void SetBit( lenVal* plv,
- int iByte,
- int iBit,
- short sVal )
+ int iByte,
+ int iBit,
+ short sVal )
{
unsigned char ucByteVal;
unsigned char ucBitMask;
@@ -166,8 +166,8 @@
* Returns: void.
*****************************************************************************/
void addVal( lenVal* plvResVal,
- lenVal* plvVal1,
- lenVal* plvVal2 )
+ lenVal* plvVal1,
+ lenVal* plvVal2 )
{
unsigned char ucCarry;
unsigned short usSum;
@@ -204,7 +204,7 @@
* Returns: void.
*****************************************************************************/
void readVal( lenVal* plv,
- short sNumBytes )
+ short sNumBytes )
{
unsigned char* pucVal;
diff --git a/board/esd/common/xilinx_jtag/micro.c b/board/esd/common/xilinx_jtag/micro.c
index f21c235..318f229 100644
--- a/board/esd/common/xilinx_jtag/micro.c
+++ b/board/esd/common/xilinx_jtag/micro.c
@@ -114,20 +114,20 @@
#ifdef DEBUG_MODE
#define XSVFDBG_PRINTF(iDebugLevel,pzFormat) \
- { if ( xsvf_iDebugLevel >= iDebugLevel ) \
- printf( pzFormat ); }
+ { if ( xsvf_iDebugLevel >= iDebugLevel ) \
+ printf( pzFormat ); }
#define XSVFDBG_PRINTF1(iDebugLevel,pzFormat,arg1) \
- { if ( xsvf_iDebugLevel >= iDebugLevel ) \
- printf( pzFormat, arg1 ); }
+ { if ( xsvf_iDebugLevel >= iDebugLevel ) \
+ printf( pzFormat, arg1 ); }
#define XSVFDBG_PRINTF2(iDebugLevel,pzFormat,arg1,arg2) \
- { if ( xsvf_iDebugLevel >= iDebugLevel ) \
- printf( pzFormat, arg1, arg2 ); }
+ { if ( xsvf_iDebugLevel >= iDebugLevel ) \
+ printf( pzFormat, arg1, arg2 ); }
#define XSVFDBG_PRINTF3(iDebugLevel,pzFormat,arg1,arg2,arg3) \
- { if ( xsvf_iDebugLevel >= iDebugLevel ) \
- printf( pzFormat, arg1, arg2, arg3 ); }
+ { if ( xsvf_iDebugLevel >= iDebugLevel ) \
+ printf( pzFormat, arg1, arg2, arg3 ); }
#define XSVFDBG_PRINTLENVAL(iDebugLevel,plenVal) \
- { if ( xsvf_iDebugLevel >= iDebugLevel ) \
- xsvfPrintLenVal(plenVal); }
+ { if ( xsvf_iDebugLevel >= iDebugLevel ) \
+ xsvfPrintLenVal(plenVal); }
#else /* !DEBUG_MODE */
#define XSVFDBG_PRINTF(iDebugLevel,pzFormat)
#define XSVFDBG_PRINTF1(iDebugLevel,pzFormat,arg1)
@@ -327,68 +327,68 @@
#ifdef DEBUG_MODE
char* xsvf_pzCommandName[] =
{
- "XCOMPLETE",
- "XTDOMASK",
- "XSIR",
- "XSDR",
- "XRUNTEST",
- "Reserved5",
- "Reserved6",
- "XREPEAT",
- "XSDRSIZE",
- "XSDRTDO",
- "XSETSDRMASKS",
- "XSDRINC",
- "XSDRB",
- "XSDRC",
- "XSDRE",
- "XSDRTDOB",
- "XSDRTDOC",
- "XSDRTDOE",
- "XSTATE",
- "XENDIR",
- "XENDDR",
- "XSIR2",
- "XCOMMENT",
- "XWAIT"
+ "XCOMPLETE",
+ "XTDOMASK",
+ "XSIR",
+ "XSDR",
+ "XRUNTEST",
+ "Reserved5",
+ "Reserved6",
+ "XREPEAT",
+ "XSDRSIZE",
+ "XSDRTDO",
+ "XSETSDRMASKS",
+ "XSDRINC",
+ "XSDRB",
+ "XSDRC",
+ "XSDRE",
+ "XSDRTDOB",
+ "XSDRTDOC",
+ "XSDRTDOE",
+ "XSTATE",
+ "XENDIR",
+ "XENDDR",
+ "XSIR2",
+ "XCOMMENT",
+ "XWAIT"
};
char* xsvf_pzErrorName[] =
{
- "No error",
- "ERROR: Unknown",
- "ERROR: TDO mismatch",
- "ERROR: TDO mismatch and exceeded max retries",
- "ERROR: Unsupported XSVF command",
- "ERROR: Illegal state specification",
- "ERROR: Data overflows allocated MAX_LEN buffer size"
+ "No error",
+ "ERROR: Unknown",
+ "ERROR: TDO mismatch",
+ "ERROR: TDO mismatch and exceeded max retries",
+ "ERROR: Unsupported XSVF command",
+ "ERROR: Illegal state specification",
+ "ERROR: Data overflows allocated MAX_LEN buffer size"
};
char* xsvf_pzTapState[] =
{
- "RESET", /* 0x00 */
- "RUNTEST/IDLE", /* 0x01 */
- "DRSELECT", /* 0x02 */
- "DRCAPTURE", /* 0x03 */
- "DRSHIFT", /* 0x04 */
- "DREXIT1", /* 0x05 */
- "DRPAUSE", /* 0x06 */
- "DREXIT2", /* 0x07 */
- "DRUPDATE", /* 0x08 */
- "IRSELECT", /* 0x09 */
- "IRCAPTURE", /* 0x0A */
- "IRSHIFT", /* 0x0B */
- "IREXIT1", /* 0x0C */
- "IRPAUSE", /* 0x0D */
- "IREXIT2", /* 0x0E */
- "IRUPDATE" /* 0x0F */
+ "RESET", /* 0x00 */
+ "RUNTEST/IDLE", /* 0x01 */
+ "DRSELECT", /* 0x02 */
+ "DRCAPTURE", /* 0x03 */
+ "DRSHIFT", /* 0x04 */
+ "DREXIT1", /* 0x05 */
+ "DRPAUSE", /* 0x06 */
+ "DREXIT2", /* 0x07 */
+ "DRUPDATE", /* 0x08 */
+ "IRSELECT", /* 0x09 */
+ "IRCAPTURE", /* 0x0A */
+ "IRSHIFT", /* 0x0B */
+ "IREXIT1", /* 0x0C */
+ "IRPAUSE", /* 0x0D */
+ "IREXIT2", /* 0x0E */
+ "IRUPDATE" /* 0x0F */
};
#endif /* DEBUG_MODE */
-//#ifdef DEBUG_MODE
-// FILE* in; /* Legacy DEBUG_MODE file pointer */
+/*#ifdef DEBUG_MODE */
+/* FILE* in; /XXX* Legacy DEBUG_MODE file pointer */
int xsvf_iDebugLevel;
-//#endif /* DEBUG_MODE */
+/*#endif /XXX* DEBUG_MODE */
/*============================================================================
* Utility Functions
@@ -493,7 +493,7 @@
* Returns: int - 0 = success; otherwise error.
*****************************************************************************/
int xsvfGotoTapState( unsigned char* pucTapState,
- unsigned char ucTargetState )
+ unsigned char ucTargetState )
{
int i;
int iErrorCode;
@@ -708,9 +708,9 @@
* Returns: void.
*****************************************************************************/
void xsvfShiftOnly( long lNumBits,
- lenVal* plvTdi,
- lenVal* plvTdoCaptured,
- int iExitShift )
+ lenVal* plvTdi,
+ lenVal* plvTdoCaptured,
+ int iExitShift )
{
unsigned char* pucTdi;
unsigned char* pucTdo;
@@ -796,15 +796,15 @@
* is NOT all zeros and sMatch==1.
*****************************************************************************/
int xsvfShift( unsigned char* pucTapState,
- unsigned char ucStartState,
- long lNumBits,
- lenVal* plvTdi,
- lenVal* plvTdoCaptured,
- lenVal* plvTdoExpected,
- lenVal* plvTdoMask,
- unsigned char ucEndState,
- long lRunTestTime,
- unsigned char ucMaxRepeat )
+ unsigned char ucStartState,
+ long lNumBits,
+ lenVal* plvTdi,
+ lenVal* plvTdoCaptured,
+ lenVal* plvTdoExpected,
+ lenVal* plvTdoMask,
+ unsigned char ucEndState,
+ long lRunTestTime,
+ unsigned char ucMaxRepeat )
{
int iErrorCode;
int iMismatch;
@@ -935,15 +935,15 @@
* Returns: int - 0 = success; otherwise TDO mismatch.
*****************************************************************************/
int xsvfBasicXSDRTDO( unsigned char* pucTapState,
- long lShiftLengthBits,
- short sShiftLengthBytes,
- lenVal* plvTdi,
- lenVal* plvTdoCaptured,
- lenVal* plvTdoExpected,
- lenVal* plvTdoMask,
- unsigned char ucEndState,
- long lRunTestTime,
- unsigned char ucMaxRepeat )
+ long lShiftLengthBits,
+ short sShiftLengthBytes,
+ lenVal* plvTdi,
+ lenVal* plvTdoCaptured,
+ lenVal* plvTdoExpected,
+ lenVal* plvTdoMask,
+ unsigned char ucEndState,
+ long lRunTestTime,
+ unsigned char ucMaxRepeat )
{
readVal( plvTdi, sShiftLengthBytes );
if ( plvTdoExpected )
@@ -968,9 +968,9 @@
*****************************************************************************/
#ifdef XSVF_SUPPORT_COMPRESSION
void xsvfDoSDRMasking( lenVal* plvTdi,
- lenVal* plvNextData,
- lenVal* plvAddressMask,
- lenVal* plvDataMask )
+ lenVal* plvNextData,
+ lenVal* plvAddressMask,
+ lenVal* plvDataMask )
{
int i;
unsigned char ucTdi;
diff --git a/board/esd/common/xilinx_jtag/micro.h b/board/esd/common/xilinx_jtag/micro.h
index a68c8d1..3c463ab 100644
--- a/board/esd/common/xilinx_jtag/micro.h
+++ b/board/esd/common/xilinx_jtag/micro.h
@@ -1,64 +1,64 @@
-/*
- * (C) Copyright 2003
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*****************************************************************************
- * File: micro.h
- * Description: This header file contains the function prototype to the
- * primary interface function for the XSVF player.
- * Usage: FIRST - PORTS.C
- * Customize the ports.c function implementations to establish
- * the correct protocol for communicating with your JTAG ports
- * (setPort() and readTDOBit()) and tune the waitTime() delay
- * function. Also, establish access to the XSVF data source
- * in the readByte() function.
- * FINALLY - Call xsvfExecute().
- *****************************************************************************/
-#ifndef XSVF_MICRO_H
-#define XSVF_MICRO_H
-
-/* Legacy error codes for xsvfExecute from original XSVF player v2.0 */
-#define XSVF_LEGACY_SUCCESS 1
-#define XSVF_LEGACY_ERROR 0
-
-/* 4.04 [NEW] Error codes for xsvfExecute. */
-/* Must #define XSVF_SUPPORT_ERRORCODES in micro.c to get these codes */
-#define XSVF_ERROR_NONE 0
-#define XSVF_ERROR_UNKNOWN 1
-#define XSVF_ERROR_TDOMISMATCH 2
-#define XSVF_ERROR_MAXRETRIES 3 /* TDO mismatch after max retries */
-#define XSVF_ERROR_ILLEGALCMD 4
-#define XSVF_ERROR_ILLEGALSTATE 5
-#define XSVF_ERROR_DATAOVERFLOW 6 /* Data > lenVal MAX_LEN buffer size*/
-/* Insert new errors here */
-#define XSVF_ERROR_LAST 7
-
-/*****************************************************************************
- * Function: xsvfExecute
- * Description: Process, interpret, and apply the XSVF commands.
- * See port.c:readByte for source of XSVF data.
- * Parameters: none.
- * Returns: int - For error codes see above.
- *****************************************************************************/
-int xsvfExecute(void);
-
-#endif /* XSVF_MICRO_H */
+/*
+ * (C) Copyright 2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*****************************************************************************
+ * File: micro.h
+ * Description: This header file contains the function prototype to the
+ * primary interface function for the XSVF player.
+ * Usage: FIRST - PORTS.C
+ * Customize the ports.c function implementations to establish
+ * the correct protocol for communicating with your JTAG ports
+ * (setPort() and readTDOBit()) and tune the waitTime() delay
+ * function. Also, establish access to the XSVF data source
+ * in the readByte() function.
+ * FINALLY - Call xsvfExecute().
+ *****************************************************************************/
+#ifndef XSVF_MICRO_H
+#define XSVF_MICRO_H
+
+/* Legacy error codes for xsvfExecute from original XSVF player v2.0 */
+#define XSVF_LEGACY_SUCCESS 1
+#define XSVF_LEGACY_ERROR 0
+
+/* 4.04 [NEW] Error codes for xsvfExecute. */
+/* Must #define XSVF_SUPPORT_ERRORCODES in micro.c to get these codes */
+#define XSVF_ERROR_NONE 0
+#define XSVF_ERROR_UNKNOWN 1
+#define XSVF_ERROR_TDOMISMATCH 2
+#define XSVF_ERROR_MAXRETRIES 3 /* TDO mismatch after max retries */
+#define XSVF_ERROR_ILLEGALCMD 4
+#define XSVF_ERROR_ILLEGALSTATE 5
+#define XSVF_ERROR_DATAOVERFLOW 6 /* Data > lenVal MAX_LEN buffer size*/
+/* Insert new errors here */
+#define XSVF_ERROR_LAST 7
+
+/*****************************************************************************
+ * Function: xsvfExecute
+ * Description: Process, interpret, and apply the XSVF commands.
+ * See port.c:readByte for source of XSVF data.
+ * Parameters: none.
+ * Returns: int - For error codes see above.
+ *****************************************************************************/
+int xsvfExecute(void);
+
+#endif /* XSVF_MICRO_H */
diff --git a/board/esd/dp405/dp405.c b/board/esd/dp405/dp405.c
index 9fc63a7..6d99b60 100644
--- a/board/esd/dp405/dp405.c
+++ b/board/esd/dp405/dp405.c
@@ -97,7 +97,7 @@
unsigned char str[64];
int i = getenv_r ("serial#", str, sizeof(str));
unsigned char trans[16] = {0x0,0x8,0x4,0xc,0x2,0xa,0x6,0xe,
- 0x1,0x9,0x5,0xd,0x3,0xb,0x7,0xf};
+ 0x1,0x9,0x5,0xd,0x3,0xb,0x7,0xf};
unsigned char id1, id2;
puts ("Board: ");
diff --git a/board/icecube/flash.c b/board/icecube/flash.c
index 07879ff..4ae71e6 100644
--- a/board/icecube/flash.c
+++ b/board/icecube/flash.c
@@ -123,7 +123,7 @@
for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
info = & flash_info[i];
- if (info->size &&
+ if (info->size &&
info->start[0] <= base && base <= info->start[0] + info->size - 1)
break;
}
@@ -260,7 +260,7 @@
addr2 = (FPW *)((ulong)addr | 0x800000);
if (addr2 != addr &&
((addr2[0] & 0xff) == (addr[0] & 0xff)) && ((FPW)addr2[1] == (FPW)addr[1])) {
- /* Seems 2 banks are the same space (8Mb chip is installed,
+ /* Seems 2 banks are the same space (8Mb chip is installed,
* J24 in default position (CS0)). Disable this (first) bank.
*/
info->flash_id = FLASH_UNKNOWN;
diff --git a/board/icecube/icecube.c b/board/icecube/icecube.c
index 965ca6b..26cce5d 100644
--- a/board/icecube/icecube.c
+++ b/board/icecube/icecube.c
@@ -174,9 +174,9 @@
void flash_afterinit(ulong size)
{
if (size == 0x800000) { /* adjust mapping */
- *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
+ *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
START_REG(CFG_BOOTCS_START | size);
- *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
+ *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
STOP_REG(CFG_BOOTCS_START | size, size);
}
}
diff --git a/board/ixdp425/u-boot.lds b/board/ixdp425/u-boot.lds
index 23f4bd0..3170aa0 100644
--- a/board/ixdp425/u-boot.lds
+++ b/board/ixdp425/u-boot.lds
@@ -26,29 +26,29 @@
ENTRY(_start)
SECTIONS
{
- . = 0x00000000;
+ . = 0x00000000;
- . = ALIGN(4);
+ . = ALIGN(4);
.text :
{
cpu/ixp/start.o (.text)
*(.text)
}
- . = ALIGN(4);
- .rodata : { *(.rodata) }
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
- . = ALIGN(4);
- .data : { *(.data) }
+ . = ALIGN(4);
+ .data : { *(.data) }
- . = ALIGN(4);
- .got : { *(.got) }
+ . = ALIGN(4);
+ .got : { *(.got) }
armboot_end_data = .;
- . = ALIGN(4);
+ . = ALIGN(4);
bss_start = .;
- .bss : { *(.bss) }
+ .bss : { *(.bss) }
bss_end = .;
armboot_end = .;
diff --git a/board/mpc8266ads/mpc8266ads.c b/board/mpc8266ads/mpc8266ads.c
index 68a59a6..e2c98b1 100644
--- a/board/mpc8266ads/mpc8266ads.c
+++ b/board/mpc8266ads/mpc8266ads.c
@@ -562,13 +562,13 @@
printf(", Using Bank Based Interleave\n");
#else
printf(", Using Page Based Interleave\n");
-#endif
+#endif
printf("\tTotal size: ");
- /* this delay only needed for original 16MB DIMM...
+ /* this delay only needed for original 16MB DIMM...
* Not needed for any other memory configuration */
if ((sdram_size * chipselects) == (16 *1024 *1024))
- udelay (250000);
+ udelay (250000);
return (sdram_size * chipselects);
/*return (16 * 1024 * 1024);*/
}
@@ -584,4 +584,3 @@
pci_mpc8250_init(&hose);
}
#endif
-
diff --git a/board/mpc8540ads/Makefile b/board/mpc8540ads/Makefile
new file mode 100644
index 0000000..d150df8
--- /dev/null
+++ b/board/mpc8540ads/Makefile
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS := $(BOARD).o flash.o
+SOBJS := init.o
+#SOBJS :=
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS)
+
+clean:
+ rm -f $(OBJS) $(SOBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/mpc8540ads/config.mk b/board/mpc8540ads/config.mk
new file mode 100644
index 0000000..186a2f2
--- /dev/null
+++ b/board/mpc8540ads/config.mk
@@ -0,0 +1,32 @@
+# Modified by Xianghua Xiao, X.Xiao@motorola.com
+# (C) Copyright 2002,Motorola Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# mpc8540ads board
+# default CCARBAR is at 0xff700000
+# assume U-Boot is less than 0.5MB
+#
+TEXT_BASE = 0xfff80000
+
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8540=1
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
diff --git a/board/mpc8540ads/flash.c b/board/mpc8540ads/flash.c
new file mode 100644
index 0000000..ac2383e
--- /dev/null
+++ b/board/mpc8540ads/flash.c
@@ -0,0 +1,539 @@
+/*
+ * (C) Copyright 2003 Motorola Inc.
+ * Xianghua Xiao,(X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
+ * Add support the Sharp chips on the mpc8260ads.
+ * I started with board/ip860/flash.c and made changes I found in
+ * the MTD project by David Schleef.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if !defined(CFG_NO_FLASH)
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+# ifndef CFG_ENV_ADDR
+# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET)
+# endif
+# ifndef CFG_ENV_SIZE
+# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
+# endif
+# ifndef CFG_ENV_SECT_SIZE
+# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE
+# endif
+#endif
+
+#undef DEBUG
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static int clear_block_lock_bit(vu_long * addr);
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+ unsigned long size;
+ int i;
+
+ /* Init: enable write,
+ * or we cannot even write flash commands
+ */
+ for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+
+ /* set the default sector offset */
+ }
+
+ /* Static FLASH Bank configuration here - FIXME XXX */
+
+ size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+ size, size<<20);
+ }
+
+ /* Re-do sizing to get full correct info */
+ size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+ flash_info[0].size = size;
+
+#if !defined(CONFIG_RAM_AS_FLASH)
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+ /* monitor protection ON by default */
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE+monitor_flash_len-1,
+ &flash_info[0]);
+#endif
+
+#ifdef CFG_ENV_IS_IN_FLASH
+ /* ENV protection ON by default */
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_ENV_ADDR,
+ CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1,
+ &flash_info[0]);
+#endif
+#endif
+ return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t *info)
+{
+ int i;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_INTEL: printf ("Intel "); break;
+ case FLASH_MAN_SHARP: printf ("Sharp "); break;
+ default: printf ("Unknown Vendor "); break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_28F016SV: printf ("28F016SV (16 Mbit, 32 x 64k)\n");
+ break;
+ case FLASH_28F160S3: printf ("28F160S3 (16 Mbit, 32 x 512K)\n");
+ break;
+ case FLASH_28F320S3: printf ("28F320S3 (32 Mbit, 64 x 512K)\n");
+ break;
+ case FLASH_LH28F016SCT: printf ("28F016SC (16 Mbit, 32 x 64K)\n");
+ break;
+ case FLASH_28F640J3A: printf ("28F640J3A (64 Mbit, 64 x 128K)\n");
+ break;
+ default: printf ("Unknown Chip Type\n");
+ break;
+ }
+
+ printf (" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
+
+ printf (" Sector Start Addresses:");
+ for (i=0; i<info->sector_count; ++i) {
+ if ((i % 5) == 0)
+ printf ("\n ");
+ printf (" %08lX%s",
+ info->start[i],
+ info->protect[i] ? " (RO)" : " "
+ );
+ }
+ printf ("\n");
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+ short i;
+ ulong value;
+ ulong base = (ulong)addr;
+ ulong sector_offset;
+
+#ifdef DEBUG
+ printf("Check flash at 0x%08x\n",(uint)addr);
+#endif
+ /* Write "Intelligent Identifier" command: read Manufacturer ID */
+ *addr = 0x90909090;
+ udelay(20);
+ asm("sync");
+
+ value = addr[0] & 0x00FF00FF;
+
+#ifdef DEBUG
+ printf("manufacturer=0x%x\n",(uint)value);
+#endif
+ switch (value) {
+ case MT_MANUFACT: /* SHARP, MT or => Intel */
+ case INTEL_ALT_MANU:
+ info->flash_id = FLASH_MAN_INTEL;
+ break;
+ default:
+ printf("unknown manufacturer: %x\n", (unsigned int)value);
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ return (0); /* no or unknown flash */
+ }
+
+ value = addr[1] & 0x00FF00FF; /* device ID */
+
+#ifdef DEBUG
+ printf("deviceID=0x%x\n",(uint)value);
+#endif
+ switch (value) {
+ case (INTEL_ID_28F016S):
+ info->flash_id += FLASH_28F016SV;
+ info->sector_count = 32;
+ info->size = 0x00400000;
+ sector_offset = 0x20000;
+ break; /* => 2x2 MB */
+
+ case (INTEL_ID_28F160S3):
+ info->flash_id += FLASH_28F160S3;
+ info->sector_count = 32;
+ info->size = 0x00400000;
+ sector_offset = 0x20000;
+ break; /* => 2x2 MB */
+
+ case (INTEL_ID_28F320S3):
+ info->flash_id += FLASH_28F320S3;
+ info->sector_count = 64;
+ info->size = 0x00800000;
+ sector_offset = 0x20000;
+ break; /* => 2x4 MB */
+
+ case (INTEL_ID_28F640J3A):
+ info->flash_id += FLASH_28F640J3A;
+ info->sector_count = 64;
+ info->size = 0x01000000;
+ sector_offset = 0x40000;
+ break; /* => 2x8 MB */
+
+ case SHARP_ID_28F016SCL:
+ case SHARP_ID_28F016SCZ:
+ info->flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT;
+ info->sector_count = 32;
+ info->size = 0x00800000;
+ sector_offset = 0x40000;
+ break; /* => 4x2 MB */
+
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ return (0); /* => no or unknown flash */
+
+ }
+
+ /* set up sector start address table */
+ for (i = 0; i < info->sector_count; i++) {
+ info->start[i] = base;
+ base += sector_offset;
+ /* don't know how to check sector protection */
+ info->protect[i] = 0;
+ }
+
+ /*
+ * Prevent writes to uninitialized FLASH.
+ */
+ if (info->flash_id != FLASH_UNKNOWN) {
+ addr = (vu_long *)info->start[0];
+ *addr = 0xFFFFFF; /* reset bank to read array mode */
+ asm("sync");
+ }
+
+ return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+ int flag, prot, sect;
+ ulong start, now, last;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("- missing\n");
+ } else {
+ printf ("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ if ( ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL)
+ && ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) {
+ printf ("Can't erase unknown flash type %08lx - aborted\n",
+ info->flash_id);
+ return 1;
+ }
+
+ prot = 0;
+ for (sect=s_first; sect<=s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf ("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf ("\n");
+ }
+
+#ifdef DEBUG
+ printf("\nFlash Erase:\n");
+#endif
+ /* Make Sure Block Lock Bit is not set. */
+ if(clear_block_lock_bit((vu_long *)(info->start[s_first]))){
+ return 1;
+ }
+
+ /* Start erase on unprotected sectors */
+#if defined(DEBUG)
+ printf("Begin to erase now,s_first=0x%x s_last=0x%x...\n",s_first,s_last);
+#endif
+ for (sect = s_first; sect<=s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ vu_long *addr = (vu_long *)(info->start[sect]);
+ asm("sync");
+
+ last = start = get_timer (0);
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ /* Reset Array */
+ *addr = 0xffffffff;
+ asm("sync");
+ /* Clear Status Register */
+ *addr = 0x50505050;
+ asm("sync");
+ /* Single Block Erase Command */
+ *addr = 0x20202020;
+ asm("sync");
+ /* Confirm */
+ *addr = 0xD0D0D0D0;
+ asm("sync");
+
+ if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) {
+ /* Resume Command, as per errata update */
+ *addr = 0xD0D0D0D0;
+ asm("sync");
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay (1000);
+ while ((*addr & 0x00800080) != 0x00800080) {
+ if(*addr & 0x00200020){
+ printf("Error in Block Erase - Lock Bit may be set!\n");
+ printf("Status Register = 0x%X\n", (uint)*addr);
+ *addr = 0xFFFFFFFF; /* reset bank */
+ asm("sync");
+ return 1;
+ }
+ if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ printf ("Timeout\n");
+ *addr = 0xFFFFFFFF; /* reset bank */
+ asm("sync");
+ return 1;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ putc ('.');
+ last = now;
+ }
+ }
+
+ /* reset to read mode */
+ *addr = 0xFFFFFFFF;
+ asm("sync");
+ }
+ }
+
+ printf ("flash erase done\n");
+ return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+ ulong cp, wp, data;
+ int i, l, rc;
+
+ wp = (addr & ~3); /* get lower word aligned address */
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+ data = 0;
+ for (i=0, cp=wp; i<l; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+ for (; i<4 && cnt>0; ++i) {
+ data = (data << 8) | *src++;
+ --cnt;
+ ++cp;
+ }
+ for (; cnt==0 && i<4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ }
+
+ /*
+ * handle word aligned part
+ */
+ while (cnt >= 4) {
+ data = 0;
+ for (i=0; i<4; ++i) {
+ data = (data << 8) | *src++;
+ }
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ cnt -= 4;
+ }
+
+ if (cnt == 0) {
+ return (0);
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+ data = (data << 8) | *src++;
+ --cnt;
+ }
+ for (; i<4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+
+ return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+ vu_long *addr = (vu_long *)dest;
+ ulong start, csr;
+ int flag;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*addr & data) != data) {
+ return (2);
+ }
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ /* Write Command */
+ *addr = 0x10101010;
+ asm("sync");
+
+ /* Write Data */
+ *addr = data;
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* data polling for D7 */
+ start = get_timer (0);
+ flag = 0;
+
+ while (((csr = *addr) & 0x00800080) != 0x00800080) {
+ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ flag = 1;
+ break;
+ }
+ }
+ if (csr & 0x40404040) {
+ printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr);
+ flag = 1;
+ }
+
+ /* Clear Status Registers Command */
+ *addr = 0x50505050;
+ asm("sync");
+ /* Reset to read array mode */
+ *addr = 0xFFFFFFFF;
+ asm("sync");
+
+ return (flag);
+}
+
+/*-----------------------------------------------------------------------
+ * Clear Block Lock Bit, returns:
+ * 0 - OK
+ * 1 - Timeout
+ */
+
+static int clear_block_lock_bit(vu_long * addr)
+{
+ ulong start, now;
+
+ /* Reset Array */
+ *addr = 0xffffffff;
+ asm("sync");
+ /* Clear Status Register */
+ *addr = 0x50505050;
+ asm("sync");
+
+ *addr = 0x60606060;
+ asm("sync");
+ *addr = 0xd0d0d0d0;
+ asm("sync");
+
+ start = get_timer (0);
+ while((*addr & 0x00800080) != 0x00800080){
+ if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ printf ("Timeout on clearing Block Lock Bit\n");
+ *addr = 0xFFFFFFFF; /* reset bank */
+ asm("sync");
+ return 1;
+ }
+ }
+ return 0;
+}
+
+#endif /* !CFG_NO_FLASH */
diff --git a/board/mpc8540ads/init.S b/board/mpc8540ads/init.S
new file mode 100644
index 0000000..8c2ca65
--- /dev/null
+++ b/board/mpc8540ads/init.S
@@ -0,0 +1,178 @@
+/*
+* Copyright (C) 2002,2003, Motorola Inc.
+* Xianghua Xiao <X.Xiao@motorola.com>
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <config.h>
+#include <mpc85xx.h>
+
+#define entry_start \
+ mflr r1 ; \
+ bl 0f ;
+
+#define entry_end \
+0: mflr r0 ; \
+ mtlr r1 ; \
+ blr ;
+
+/* TLB1 entries configuration: */
+
+ .section .bootpg, "ax"
+ .globl tlb1_entry
+tlb1_entry:
+ entry_start
+
+ .long 0x0a /* the following data table uses a few of 16 TLB entries */
+
+ .long TLB1_MAS0(1,1,0)
+ .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
+ .long TLB1_MAS2(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+ #if defined(CFG_FLASH_PORT_WIDTH_16)
+ .long TLB1_MAS0(1,2,0)
+ .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
+ .long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(1,3,0)
+ .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
+ .long TLB1_MAS2((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,0,1,0,1,0,1)
+ #else
+ .long TLB1_MAS0(1,2,0)
+ .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16M)
+ .long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(1,3,0)
+ .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+ .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+ #endif
+
+ #if !defined(CONFIG_SPD_EEPROM)
+ .long TLB1_MAS0(1,4,0)
+ .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
+ .long TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(1,5,0)
+ .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
+ .long TLB1_MAS2((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+ #else
+ .long TLB1_MAS0(1,4,0)
+ .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+ .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(1,5,0)
+ .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+ .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+ #endif
+
+ .long TLB1_MAS0(1,6,0)
+ .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
+ #if defined(CONFIG_RAM_AS_FLASH)
+ .long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+ #else
+ .long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
+ #endif
+ .long TLB1_MAS3(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(1,7,0)
+ .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
+ #ifdef CONFIG_L2_INIT_RAM
+ .long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,1,0,0,0,0)
+ #else
+ .long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,0,0,0)
+ #endif
+ .long TLB1_MAS3(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(1,8,0)
+ .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
+ .long TLB1_MAS2(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(1,9,0)
+ .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
+ .long TLB1_MAS2(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+ #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+ .long TLB1_MAS0(1,15,0)
+ .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
+ .long TLB1_MAS2(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+ #else
+ .long TLB1_MAS0(1,15,0)
+ .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+ .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+ #endif
+ entry_end
+
+/* LAW(Local Access Window) configuration:
+ * 0000_0000-0800_0000: DDR(128M) -or- larger
+ * f000_0000-f3ff_ffff: PCI(256M)
+ * f400_0000-f7ff_ffff: RapidIO(128M)
+ * f800_0000-ffff_ffff: localbus(128M)
+ * f800_0000-fbff_ffff: LBC SDRAM(64M)
+ * fc00_0000-fdef_ffff: LBC BCSR,RTC,etc(31M)
+ * fdf0_0000-fdff_ffff: CCSRBAR(1M)
+ * fe00_0000-ffff_ffff: Flash(32M)
+ * Note: CCSRBAR and L2-as-SRAM don't need configure Local Access
+ * Window.
+ * Note: If flash is 8M at default position(last 8M),no LAW needed.
+ */
+
+#if !defined(CONFIG_SPD_EEPROM)
+#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M))
+#else
+#define LAWBAR0 0
+#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
+#endif
+
+#define LAWBAR1 ((CFG_PCI_MEM_BASE>>12) & 0xfffff)
+#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+#if !defined(CONFIG_RAM_AS_FLASH)
+#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M))
+#else
+#define LAWBAR2 0
+#define LAWAR2 ((LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
+#endif
+
+ .section .bootpg, "ax"
+ .globl law_entry
+law_entry:
+ entry_start
+ .long 0x03
+ .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2
+ entry_end
diff --git a/board/mpc8540ads/mpc8540ads.c b/board/mpc8540ads/mpc8540ads.c
new file mode 100644
index 0000000..c21cd9e
--- /dev/null
+++ b/board/mpc8540ads/mpc8540ads.c
@@ -0,0 +1,265 @@
+/*
+ * (C) Copyright 2002,2003, Motorola Inc.
+ * Xianghua Xiao, (X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+extern long int spd_sdram (void);
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <spd.h>
+
+long int fixed_sdram (void);
+
+/* MPC8540ADS Board Status & Control Registers */
+#if 0
+typedef struct bscr_ {
+ unsigned long bcsr0;
+ unsigned long bcsr1;
+ unsigned long bcsr2;
+ unsigned long bcsr3;
+ unsigned long bcsr4;
+ unsigned long bcsr5;
+ unsigned long bcsr6;
+ unsigned long bcsr7;
+} bcsr_t;
+#endif
+
+int board_pre_init (void)
+{
+#if defined(CONFIG_PCI)
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile ccsr_pcix_t *pci = &immr->im_pcix;
+
+ pci->peer &= 0xffffffdf; /* disable master abort */
+#endif
+ return 0;
+}
+
+int checkboard (void)
+{
+ sys_info_t sysinfo;
+
+ get_sys_info (&sysinfo);
+
+ printf ("Board: Motorola MPC8540ADS Board\n");
+ printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
+ printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000);
+ printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000);
+ if((CFG_LBC_LCRR & 0x0f) == 2 || (CFG_LBC_LCRR & 0x0f) == 4 \
+ || (CFG_LBC_LCRR & 0x0f) == 8) {
+ printf ("\tLBC: %lu MHz\n", sysinfo.freqSystemBus / 1000000 /(CFG_LBC_LCRR & 0x0f));
+ } else {
+ printf("\tLBC: unknown\n");
+ }
+ printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n");
+ return (0);
+}
+
+long int initdram (int board_type)
+{
+ long dram_size = 0;
+ extern long spd_sdram (void);
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+#if !defined(CONFIG_RAM_AS_FLASH)
+ volatile ccsr_lbc_t *lbc= &immap->im_lbc;
+ sys_info_t sysinfo;
+ uint temp_lbcdll = 0;
+#endif
+#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
+ volatile ccsr_gur_t *gur= &immap->im_gur;
+#endif
+#if defined(CONFIG_DDR_DLL)
+ uint temp_ddrdll = 0;
+
+ /* Work around to stabilize DDR DLL */
+ temp_ddrdll = gur->ddrdllcr;
+ gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
+ asm("sync;isync;msync");
+#endif
+
+#if defined(CONFIG_SPD_EEPROM)
+ dram_size = spd_sdram ();
+#else
+ dram_size = fixed_sdram ();
+#endif
+
+#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus is not emulating flash */
+ get_sys_info(&sysinfo);
+ /* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */
+ if(sysinfo.freqSystemBus/(CFG_LBC_LCRR & 0x0f) < 66000000) {
+ lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff)| 0x80000000;
+ } else {
+#if defined(CONFIG_MPC85xx_REV1) /* need change CLKDIV before enable DLL */
+ lbc->lcrr = 0x10000004; /* default CLKDIV is 8, change it to 4 temporarily */
+#endif
+ lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff;
+ udelay(200);
+ temp_lbcdll = gur->lbcdllcr;
+ gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
+ asm("sync;isync;msync");
+ }
+ lbc->or2 = CFG_OR2_PRELIM; /* 64MB SDRAM */
+ lbc->br2 = CFG_BR2_PRELIM;
+ lbc->lbcr = CFG_LBC_LBCR;
+ lbc->lsdmr = CFG_LBC_LSDMR_1;
+ asm("sync");
+ (unsigned int) * (ulong *)0 = 0x000000ff;
+ lbc->lsdmr = CFG_LBC_LSDMR_2;
+ asm("sync");
+ (unsigned int) * (ulong *)0 = 0x000000ff;
+ lbc->lsdmr = CFG_LBC_LSDMR_3;
+ asm("sync");
+ (unsigned int) * (ulong *)0 = 0x000000ff;
+ lbc->lsdmr = CFG_LBC_LSDMR_4;
+ asm("sync");
+ (unsigned int) * (ulong *)0 = 0x000000ff;
+ lbc->lsdmr = CFG_LBC_LSDMR_5;
+ asm("sync");
+ lbc->lsrt = CFG_LBC_LSRT;
+ asm("sync");
+ lbc->mrtpr = CFG_LBC_MRTPR;
+ asm("sync");
+#endif
+
+#if defined(CONFIG_DDR_ECC)
+ {
+ /* Initialize all of memory for ECC, then
+ * enable errors */
+ uint *p = 0;
+ uint i = 0;
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+ dma_init();
+ for (*p = 0; p < (uint *)(8 * 1024); p++) {
+ if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
+ *p = (unsigned int)0xdeadbeef;
+ if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); }
+ }
+
+ /* 8K */
+ dma_xfer((uint *)0x2000,0x2000,(uint *)0);
+ /* 16K */
+ dma_xfer((uint *)0x4000,0x4000,(uint *)0);
+ /* 32K */
+ dma_xfer((uint *)0x8000,0x8000,(uint *)0);
+ /* 64K */
+ dma_xfer((uint *)0x10000,0x10000,(uint *)0);
+ /* 128k */
+ dma_xfer((uint *)0x20000,0x20000,(uint *)0);
+ /* 256k */
+ dma_xfer((uint *)0x40000,0x40000,(uint *)0);
+ /* 512k */
+ dma_xfer((uint *)0x80000,0x80000,(uint *)0);
+ /* 1M */
+ dma_xfer((uint *)0x100000,0x100000,(uint *)0);
+ /* 2M */
+ dma_xfer((uint *)0x200000,0x200000,(uint *)0);
+ /* 4M */
+ dma_xfer((uint *)0x400000,0x400000,(uint *)0);
+
+ for (i = 1; i < dram_size / 0x800000; i++) {
+ dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0);
+ }
+
+ /* Enable errors for ECC */
+ ddr->err_disable = 0x00000000;
+ asm("sync;isync;msync");
+ }
+#endif
+
+ return dram_size;
+}
+
+
+#if defined(CFG_DRAM_TEST)
+int testdram (void)
+{
+ uint *pstart = (uint *) CFG_MEMTEST_START;
+ uint *pend = (uint *) CFG_MEMTEST_END;
+ uint *p;
+
+ printf("SDRAM test phase 1:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0xaaaaaaaa;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0xaaaaaaaa) {
+ printf ("SDRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf("SDRAM test phase 2:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0x55555555;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0x55555555) {
+ printf ("SDRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf("SDRAM test passed.\n");
+ return 0;
+}
+#endif
+
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ * fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+long int fixed_sdram (void)
+{
+ #ifndef CFG_RAMBOOT
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+
+ ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
+ ddr->cs0_config = CFG_DDR_CS0_CONFIG;
+ ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
+ ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
+ ddr->sdram_mode = CFG_DDR_MODE;
+ ddr->sdram_interval = CFG_DDR_INTERVAL;
+ #if defined (CONFIG_DDR_ECC)
+ ddr->err_disable = 0x0000000D;
+ ddr->err_sbe = 0x00ff0000;
+ #endif
+ asm("sync;isync;msync");
+ udelay(500);
+ #if defined (CONFIG_DDR_ECC)
+ /* Enable ECC checking */
+ ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
+ #else
+ ddr->sdram_cfg = CFG_DDR_CONTROL;
+ #endif
+ asm("sync; isync; msync");
+ udelay(500);
+ #endif
+ return (CFG_SDRAM_SIZE * 1024 * 1024);
+}
+#endif /* !defined(CONFIG_SPD_EEPROM) */
diff --git a/board/mpc8540ads/u-boot.lds b/board/mpc8540ads/u-boot.lds
new file mode 100644
index 0000000..56dd457
--- /dev/null
+++ b/board/mpc8540ads/u-boot.lds
@@ -0,0 +1,148 @@
+/*
+ * (C) Copyright 2002,2003, Motorola,Inc.
+ * Xianghua Xiao, X.Xiao@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ .bootpg 0xFFFFF000 :
+ {
+ cpu/mpc85xx/start.o (.bootpg)
+ board/mpc8540ads/init.o (.bootpg)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/mpc85xx/start.o (.text)
+ board/mpc8540ads/init.o (.text)
+ cpu/mpc85xx/traps.o (.text)
+ cpu/mpc85xx/interrupts.o (.text)
+ cpu/mpc85xx/cpu_init.o (.text)
+ cpu/mpc85xx/cpu.o (.text)
+ cpu/mpc85xx/tsec.o (.text)
+ cpu/mpc85xx/speed.o (.text)
+ cpu/mpc85xx/pci.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_ppc/extable.o (.text)
+ lib_generic/zlib.o (.text)
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/mpc8560ads/Makefile b/board/mpc8560ads/Makefile
new file mode 100644
index 0000000..d150df8
--- /dev/null
+++ b/board/mpc8560ads/Makefile
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS := $(BOARD).o flash.o
+SOBJS := init.o
+#SOBJS :=
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS)
+
+clean:
+ rm -f $(OBJS) $(SOBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/mpc8560ads/config.mk b/board/mpc8560ads/config.mk
new file mode 100644
index 0000000..698fdaa
--- /dev/null
+++ b/board/mpc8560ads/config.mk
@@ -0,0 +1,32 @@
+# Modified by Xianghua Xiao, X.Xiao@motorola.com
+# (C) Copyright 2002,2003 Motorola Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# mpc8560ads board
+# default CCARBAR is at 0xff700000
+# assume U-Boot is less than 0.5MB
+#
+TEXT_BASE = 0xfff80000
+
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8560=1
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
diff --git a/board/mpc8560ads/flash.c b/board/mpc8560ads/flash.c
new file mode 100644
index 0000000..c9dfb4d
--- /dev/null
+++ b/board/mpc8560ads/flash.c
@@ -0,0 +1,539 @@
+/*
+ * (C) Copyright 2003 Motorola Inc.
+ * Xianghua Xiao,(X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
+ * Add support the Sharp chips on the mpc8260ads.
+ * I started with board/ip860/flash.c and made changes I found in
+ * the MTD project by David Schleef.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if !defined(CFG_NO_FLASH)
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+# ifndef CFG_ENV_ADDR
+# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET)
+# endif
+# ifndef CFG_ENV_SIZE
+# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
+# endif
+# ifndef CFG_ENV_SECT_SIZE
+# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE
+# endif
+#endif
+
+#undef DEBUG
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static int clear_block_lock_bit(vu_long * addr);
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+ unsigned long size;
+ int i;
+
+ /* Init: enable write,
+ * or we cannot even write flash commands
+ */
+ for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+
+ /* set the default sector offset */
+ }
+
+ /* Static FLASH Bank configuration here - FIXME XXX */
+
+ size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+ size, size<<20);
+ }
+
+ /* Re-do sizing to get full correct info */
+ size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+ flash_info[0].size = size;
+
+#if !defined(CONFIG_RAM_AS_FLASH)
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+ /* monitor protection ON by default */
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE+monitor_flash_len-1,
+ &flash_info[0]);
+#endif
+
+#ifdef CFG_ENV_IS_IN_FLASH
+ /* ENV protection ON by default */
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_ENV_ADDR,
+ CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1,
+ &flash_info[0]);
+#endif
+#endif
+ return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t *info)
+{
+ int i;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_INTEL: printf ("Intel "); break;
+ case FLASH_MAN_SHARP: printf ("Sharp "); break;
+ default: printf ("Unknown Vendor "); break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_28F016SV: printf ("28F016SV (16 Mbit, 32 x 64k)\n");
+ break;
+ case FLASH_28F160S3: printf ("28F160S3 (16 Mbit, 32 x 512K)\n");
+ break;
+ case FLASH_28F320S3: printf ("28F320S3 (32 Mbit, 64 x 512K)\n");
+ break;
+ case FLASH_LH28F016SCT: printf ("28F016SC (16 Mbit, 32 x 64K)\n");
+ break;
+ case FLASH_28F640J3A: printf ("28F640J3A (64 Mbit, 64 x 128K)\n");
+ break;
+ default: printf ("Unknown Chip Type\n");
+ break;
+ }
+
+ printf (" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
+
+ printf (" Sector Start Addresses:");
+ for (i=0; i<info->sector_count; ++i) {
+ if ((i % 5) == 0)
+ printf ("\n ");
+ printf (" %08lX%s",
+ info->start[i],
+ info->protect[i] ? " (RO)" : " "
+ );
+ }
+ printf ("\n");
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+ short i;
+ ulong value;
+ ulong base = (ulong)addr;
+ ulong sector_offset;
+
+#ifdef DEBUG
+ printf("Check flash at 0x%08x\n",(uint)addr);
+#endif
+ /* Write "Intelligent Identifier" command: read Manufacturer ID */
+ *addr = 0x90909090;
+ udelay(20);
+ asm("sync");
+
+ value = addr[0] & 0x00FF00FF;
+
+#ifdef DEBUG
+ printf("manufacturer=0x%x\n",(uint)value);
+#endif
+ switch (value) {
+ case MT_MANUFACT: /* SHARP, MT or => Intel */
+ case INTEL_ALT_MANU:
+ info->flash_id = FLASH_MAN_INTEL;
+ break;
+ default:
+ printf("unknown manufacturer: %x\n", (unsigned int)value);
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ return (0); /* no or unknown flash */
+ }
+
+ value = addr[1] & 0x00FF00FF; /* device ID */
+
+#ifdef DEBUG
+ printf("deviceID=0x%x\n",(uint)value);
+#endif
+ switch (value) {
+ case (INTEL_ID_28F016S):
+ info->flash_id += FLASH_28F016SV;
+ info->sector_count = 32;
+ info->size = 0x00400000;
+ sector_offset = 0x20000;
+ break; /* => 2x2 MB */
+
+ case (INTEL_ID_28F160S3):
+ info->flash_id += FLASH_28F160S3;
+ info->sector_count = 32;
+ info->size = 0x00400000;
+ sector_offset = 0x20000;
+ break; /* => 2x2 MB */
+
+ case (INTEL_ID_28F320S3):
+ info->flash_id += FLASH_28F320S3;
+ info->sector_count = 64;
+ info->size = 0x00800000;
+ sector_offset = 0x20000;
+ break; /* => 2x4 MB */
+
+ case (INTEL_ID_28F640J3A):
+ info->flash_id += FLASH_28F640J3A;
+ info->sector_count = 64;
+ info->size = 0x01000000;
+ sector_offset = 0x40000;
+ break; /* => 8 MB */
+
+ case SHARP_ID_28F016SCL:
+ case SHARP_ID_28F016SCZ:
+ info->flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT;
+ info->sector_count = 32;
+ info->size = 0x00800000;
+ sector_offset = 0x40000;
+ break; /* => 4x2 MB */
+
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ return (0); /* => no or unknown flash */
+
+ }
+
+ /* set up sector start address table */
+ for (i = 0; i < info->sector_count; i++) {
+ info->start[i] = base;
+ base += sector_offset;
+ /* don't know how to check sector protection */
+ info->protect[i] = 0;
+ }
+
+ /*
+ * Prevent writes to uninitialized FLASH.
+ */
+ if (info->flash_id != FLASH_UNKNOWN) {
+ addr = (vu_long *)info->start[0];
+ *addr = 0xFFFFFF; /* reset bank to read array mode */
+ asm("sync");
+ }
+
+ return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+ int flag, prot, sect;
+ ulong start, now, last;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("- missing\n");
+ } else {
+ printf ("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ if ( ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL)
+ && ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) {
+ printf ("Can't erase unknown flash type %08lx - aborted\n",
+ info->flash_id);
+ return 1;
+ }
+
+ prot = 0;
+ for (sect=s_first; sect<=s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf ("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf ("\n");
+ }
+
+#ifdef DEBUG
+ printf("\nFlash Erase:\n");
+#endif
+ /* Make Sure Block Lock Bit is not set. */
+ if(clear_block_lock_bit((vu_long *)(info->start[s_first]))){
+ return 1;
+ }
+
+ /* Start erase on unprotected sectors */
+#if defined(DEBUG)
+ printf("Begin to erase now,s_first=0x%x s_last=0x%x...\n",s_first,s_last);
+#endif
+ for (sect = s_first; sect<=s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ vu_long *addr = (vu_long *)(info->start[sect]);
+ asm("sync");
+
+ last = start = get_timer (0);
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ /* Reset Array */
+ *addr = 0xffffffff;
+ asm("sync");
+ /* Clear Status Register */
+ *addr = 0x50505050;
+ asm("sync");
+ /* Single Block Erase Command */
+ *addr = 0x20202020;
+ asm("sync");
+ /* Confirm */
+ *addr = 0xD0D0D0D0;
+ asm("sync");
+
+ if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) {
+ /* Resume Command, as per errata update */
+ *addr = 0xD0D0D0D0;
+ asm("sync");
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay (1000);
+ while ((*addr & 0x00800080) != 0x00800080) {
+ if(*addr & 0x00200020){
+ printf("Error in Block Erase - Lock Bit may be set!\n");
+ printf("Status Register = 0x%X\n", (uint)*addr);
+ *addr = 0xFFFFFFFF; /* reset bank */
+ asm("sync");
+ return 1;
+ }
+ if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ printf ("Timeout\n");
+ *addr = 0xFFFFFFFF; /* reset bank */
+ asm("sync");
+ return 1;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ putc ('.');
+ last = now;
+ }
+ }
+
+ /* reset to read mode */
+ *addr = 0xFFFFFFFF;
+ asm("sync");
+ }
+ }
+
+ printf ("flash erase done\n");
+ return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+ ulong cp, wp, data;
+ int i, l, rc;
+
+ wp = (addr & ~3); /* get lower word aligned address */
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+ data = 0;
+ for (i=0, cp=wp; i<l; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+ for (; i<4 && cnt>0; ++i) {
+ data = (data << 8) | *src++;
+ --cnt;
+ ++cp;
+ }
+ for (; cnt==0 && i<4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ }
+
+ /*
+ * handle word aligned part
+ */
+ while (cnt >= 4) {
+ data = 0;
+ for (i=0; i<4; ++i) {
+ data = (data << 8) | *src++;
+ }
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ cnt -= 4;
+ }
+
+ if (cnt == 0) {
+ return (0);
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+ data = (data << 8) | *src++;
+ --cnt;
+ }
+ for (; i<4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+
+ return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+ vu_long *addr = (vu_long *)dest;
+ ulong start, csr;
+ int flag;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*addr & data) != data) {
+ return (2);
+ }
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ /* Write Command */
+ *addr = 0x10101010;
+ asm("sync");
+
+ /* Write Data */
+ *addr = data;
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* data polling for D7 */
+ start = get_timer (0);
+ flag = 0;
+
+ while (((csr = *addr) & 0x00800080) != 0x00800080) {
+ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ flag = 1;
+ break;
+ }
+ }
+ if (csr & 0x40404040) {
+ printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr);
+ flag = 1;
+ }
+
+ /* Clear Status Registers Command */
+ *addr = 0x50505050;
+ asm("sync");
+ /* Reset to read array mode */
+ *addr = 0xFFFFFFFF;
+ asm("sync");
+
+ return (flag);
+}
+
+/*-----------------------------------------------------------------------
+ * Clear Block Lock Bit, returns:
+ * 0 - OK
+ * 1 - Timeout
+ */
+
+static int clear_block_lock_bit(vu_long * addr)
+{
+ ulong start, now;
+
+ /* Reset Array */
+ *addr = 0xffffffff;
+ asm("sync");
+ /* Clear Status Register */
+ *addr = 0x50505050;
+ asm("sync");
+
+ *addr = 0x60606060;
+ asm("sync");
+ *addr = 0xd0d0d0d0;
+ asm("sync");
+
+ start = get_timer (0);
+ while((*addr & 0x00800080) != 0x00800080){
+ if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ printf ("Timeout on clearing Block Lock Bit\n");
+ *addr = 0xFFFFFFFF; /* reset bank */
+ asm("sync");
+ return 1;
+ }
+ }
+ return 0;
+}
+
+#endif /* !CFG_NO_FLASH */
diff --git a/board/mpc8560ads/init.S b/board/mpc8560ads/init.S
new file mode 100644
index 0000000..c716ef1
--- /dev/null
+++ b/board/mpc8560ads/init.S
@@ -0,0 +1,178 @@
+/*
+* Copyright (C) 2002,2003, Motorola Inc.
+* Xianghua Xiao <X.Xiao@motorola.com>
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <config.h>
+#include <mpc85xx.h>
+
+#define entry_start \
+ mflr r1 ; \
+ bl 0f ;
+
+#define entry_end \
+0: mflr r0 ; \
+ mtlr r1 ; \
+ blr ;
+
+/* TLB1 entries configuration: */
+
+ .section .bootpg, "ax"
+ .globl tlb1_entry
+tlb1_entry:
+ entry_start
+
+ .long 0x0a /* the following data table uses a few of 16 TLB entries */
+
+ .long TLB1_MAS0(1,1,0)
+ .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
+ .long TLB1_MAS2(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+ #if defined(CFG_FLASH_PORT_WIDTH_16)
+ .long TLB1_MAS0(1,2,0)
+ .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
+ .long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(1,3,0)
+ .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
+ .long TLB1_MAS2((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,0,1,0,1,0,1)
+ #else
+ .long TLB1_MAS0(1,2,0)
+ .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16M)
+ .long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(1,3,0)
+ .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+ .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+ #endif
+
+ #if !defined(CONFIG_SPD_EEPROM)
+ .long TLB1_MAS0(1,4,0)
+ .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
+ .long TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(1,5,0)
+ .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
+ .long TLB1_MAS2((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+ #else
+ .long TLB1_MAS0(1,4,0)
+ .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+ .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(1,5,0)
+ .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+ .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+ #endif
+
+ .long TLB1_MAS0(1,6,0)
+ .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
+ #if defined(CONFIG_RAM_AS_FLASH)
+ .long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+ #else
+ .long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
+ #endif
+ .long TLB1_MAS3(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(1,7,0)
+ .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
+ #ifdef CONFIG_L2_INIT_RAM
+ .long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,1,0,0,0,0)
+ #else
+ .long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,0,0,0)
+ #endif
+ .long TLB1_MAS3(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(1,8,0)
+ .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
+ .long TLB1_MAS2(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(1,9,0)
+ .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
+ .long TLB1_MAS2(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+ #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+ .long TLB1_MAS0(1,15,0)
+ .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
+ .long TLB1_MAS2(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+ #else
+ .long TLB1_MAS0(1,15,0)
+ .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+ .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+ #endif
+ entry_end
+
+/* LAW(Local Access Window) configuration:
+ * 0000_0000-0800_0000: DDR(128M) -or- larger
+ * f000_0000-f3ff_ffff: PCI(256M)
+ * f400_0000-f7ff_ffff: RapidIO(128M)
+ * f800_0000-ffff_ffff: localbus(128M)
+ * f800_0000-fbff_ffff: LBC SDRAM(64M)
+ * fc00_0000-fdef_ffff: LBC BCSR,RTC,etc(31M)
+ * fdf0_0000-fdff_ffff: CCSRBAR(1M)
+ * fe00_0000-ffff_ffff: Flash(32M)
+ * Note: CCSRBAR and L2-as-SRAM don't need configure Local Access
+ * Window.
+ * Note: If flash is 8M at default position(last 8M),no LAW needed.
+ */
+
+#if !defined(CONFIG_SPD_EEPROM)
+#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M))
+#else
+#define LAWBAR0 0
+#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
+#endif
+
+#define LAWBAR1 ((CFG_PCI_MEM_BASE>>12) & 0xfffff)
+#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+#if !defined(CONFIG_RAM_AS_FLASH)
+#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M))
+#else
+#define LAWBAR2 0
+#define LAWAR2 ((LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
+#endif
+
+ .section .bootpg, "ax"
+ .globl law_entry
+law_entry:
+ entry_start
+ .long 0x03
+ .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2
+ entry_end
diff --git a/board/mpc8560ads/mpc8560ads.c b/board/mpc8560ads/mpc8560ads.c
new file mode 100644
index 0000000..5567b69
--- /dev/null
+++ b/board/mpc8560ads/mpc8560ads.c
@@ -0,0 +1,445 @@
+/*
+ * (C) Copyright 2003,Motorola Inc.
+ * Xianghua Xiao, (X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+extern long int spd_sdram (void);
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <ioports.h>
+#include <spd.h>
+#include <miiphy.h>
+
+long int fixed_sdram (void);
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+ /* Port A configuration */
+ { /* conf ppar psor pdir podr pdat */
+ /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
+ /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
+ /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
+ /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
+ /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
+ /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
+ /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
+ /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
+ /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
+ /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
+ /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
+ /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
+ /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
+ /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
+ /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
+ /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
+ /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
+ /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
+ /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
+ /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
+ /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
+ /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
+ /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
+ /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
+ /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
+ /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
+ /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
+ /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
+ /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
+ /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
+ /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
+ /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
+ },
+
+ /* Port B configuration */
+ { /* conf ppar psor pdir podr pdat */
+ /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
+ /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
+ /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
+ /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
+ /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
+ /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
+ /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
+ /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
+ /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
+ /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
+ /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
+ /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
+ /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
+ /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
+ /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
+ /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
+ /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
+ /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
+ /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
+ /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
+ /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
+ },
+
+ /* Port C */
+ { /* conf ppar psor pdir podr pdat */
+ /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
+ /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
+ /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
+ /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
+ /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
+ /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
+ /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
+ /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
+ /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
+ /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
+ /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
+ /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
+ /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
+ /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
+ /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
+ /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
+ /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */
+ /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
+ /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
+ /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
+ /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
+ /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
+ /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
+ /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
+ /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
+ /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
+ /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
+ /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
+ /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
+ /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
+ /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
+ /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
+ },
+
+ /* Port D */
+ { /* conf ppar psor pdir podr pdat */
+ /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
+ /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
+ /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
+ /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
+ /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
+ /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
+ /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
+ /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
+ /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
+ /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
+ /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
+ /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
+ /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
+ /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
+ /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
+ /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
+ /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
+ /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */
+ /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
+ /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
+ /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
+ /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
+ /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
+ /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
+ /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
+ /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
+ /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
+ /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
+ /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
+ }
+};
+
+/* MPC8560ADS Board Status & Control Registers */
+typedef struct bscr_ {
+ volatile unsigned char bcsr0;
+ volatile unsigned char bcsr1;
+ volatile unsigned char bcsr2;
+ volatile unsigned char bcsr3;
+ volatile unsigned char bcsr4;
+ volatile unsigned char bcsr5;
+} bcsr_t;
+
+int board_pre_init (void)
+{
+#if defined(CONFIG_PCI)
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile ccsr_pcix_t *pci = &immr->im_pcix;
+
+ pci->peer &= 0xfffffffdf; /* disable master abort */
+#endif
+ return 0;
+}
+
+void reset_phy (void)
+{
+#if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */
+ volatile bcsr_t *bcsr = (bcsr_t *) CFG_BCSR;
+#endif
+ /* reset Giga bit Ethernet port if needed here */
+
+ /* reset the CPM FEC port */
+#if (CONFIG_ETHER_INDEX == 2)
+ bcsr->bcsr2 &= ~FETH2_RST;
+ udelay(2);
+ bcsr->bcsr2 |= FETH2_RST;
+ udelay(1000);
+#elif (CONFIG_ETHER_INDEX == 3)
+ bcsr->bcsr3 &= ~FETH3_RST;
+ udelay(2);
+ bcsr->bcsr3 |= FETH3_RST;
+ udelay(1000);
+#endif
+#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
+ miiphy_reset(0x0); /* reset PHY */
+ miiphy_write(0, PHY_MIPSCR, 0xf028); /* change PHY address to 0x02 */
+ miiphy_write(0x02, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
+#endif /* CONFIG_MII */
+}
+
+int checkboard (void)
+{
+ sys_info_t sysinfo;
+
+ get_sys_info (&sysinfo);
+
+ printf ("Board: Motorola MPC8560ADS Board\n");
+ printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
+ printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000);
+ printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000);
+ if((CFG_LBC_LCRR & 0x0f) == 2 || (CFG_LBC_LCRR & 0x0f) == 4 \
+ || (CFG_LBC_LCRR & 0x0f) == 8) {
+ printf ("\tLBC: %lu MHz\n", sysinfo.freqSystemBus / 1000000 /(CFG_LBC_LCRR & 0x0f));
+ } else {
+ printf("\tLBC: unknown\n");
+ }
+ printf("\tCPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000);
+ printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n");
+
+ return (0);
+}
+
+
+long int initdram (int board_type)
+{
+ long dram_size = 0;
+ extern long spd_sdram (void);
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+#if !defined(CONFIG_RAM_AS_FLASH)
+ volatile ccsr_lbc_t *lbc= &immap->im_lbc;
+ sys_info_t sysinfo;
+ uint temp_lbcdll = 0;
+#endif
+#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
+ volatile ccsr_gur_t *gur= &immap->im_gur;
+#endif
+#if defined(CONFIG_DDR_DLL)
+ uint temp_ddrdll = 0;
+
+ /* Work around to stabilize DDR DLL */
+ temp_ddrdll = gur->ddrdllcr;
+ gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
+ asm("sync;isync;msync");
+#endif
+
+#if defined(CONFIG_SPD_EEPROM)
+ dram_size = spd_sdram ();
+#else
+ dram_size = fixed_sdram ();
+#endif
+
+#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus SDRAM is not emulating flash */
+ get_sys_info(&sysinfo);
+ /* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */
+ if(sysinfo.freqSystemBus/(CFG_LBC_LCRR & 0x0f) < 66000000) {
+ lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff)| 0x80000000;
+ } else {
+#if defined(CONFIG_MPC85xx_REV1) /* need change CLKDIV before enable DLL */
+ lbc->lcrr = 0x10000004; /* default CLKDIV is 8, change it to 4 temporarily */
+#endif
+ lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff;
+ udelay(200);
+ temp_lbcdll = gur->lbcdllcr;
+ gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
+ asm("sync;isync;msync");
+ }
+ lbc->or2 = CFG_OR2_PRELIM; /* 64MB SDRAM */
+ lbc->br2 = CFG_BR2_PRELIM;
+ lbc->lbcr = CFG_LBC_LBCR;
+ lbc->lsdmr = CFG_LBC_LSDMR_1;
+ asm("sync");
+ (unsigned int) * (ulong *)0 = 0x000000ff;
+ lbc->lsdmr = CFG_LBC_LSDMR_2;
+ asm("sync");
+ (unsigned int) * (ulong *)0 = 0x000000ff;
+ lbc->lsdmr = CFG_LBC_LSDMR_3;
+ asm("sync");
+ (unsigned int) * (ulong *)0 = 0x000000ff;
+ lbc->lsdmr = CFG_LBC_LSDMR_4;
+ asm("sync");
+ (unsigned int) * (ulong *)0 = 0x000000ff;
+ lbc->lsdmr = CFG_LBC_LSDMR_5;
+ asm("sync");
+ lbc->lsrt = CFG_LBC_LSRT;
+ asm("sync");
+ lbc->mrtpr = CFG_LBC_MRTPR;
+ asm("sync");
+#endif
+
+#if defined(CONFIG_DDR_ECC)
+ {
+ /* Initialize all of memory for ECC, then
+ * enable errors */
+ uint *p = 0;
+ uint i = 0;
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+ dma_init();
+ for (*p = 0; p < (uint *)(8 * 1024); p++) {
+ if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
+ *p = (unsigned int)0xdeadbeef;
+ if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); }
+ }
+
+ /* 8K */
+ dma_xfer((uint *)0x2000,0x2000,(uint *)0);
+ /* 16K */
+ dma_xfer((uint *)0x4000,0x4000,(uint *)0);
+ /* 32K */
+ dma_xfer((uint *)0x8000,0x8000,(uint *)0);
+ /* 64K */
+ dma_xfer((uint *)0x10000,0x10000,(uint *)0);
+ /* 128k */
+ dma_xfer((uint *)0x20000,0x20000,(uint *)0);
+ /* 256k */
+ dma_xfer((uint *)0x40000,0x40000,(uint *)0);
+ /* 512k */
+ dma_xfer((uint *)0x80000,0x80000,(uint *)0);
+ /* 1M */
+ dma_xfer((uint *)0x100000,0x100000,(uint *)0);
+ /* 2M */
+ dma_xfer((uint *)0x200000,0x200000,(uint *)0);
+ /* 4M */
+ dma_xfer((uint *)0x400000,0x400000,(uint *)0);
+
+ for (i = 1; i < dram_size / 0x800000; i++) {
+ dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0);
+ }
+
+ /* Enable errors for ECC */
+ ddr->err_disable = 0x00000000;
+ asm("sync;isync;msync");
+ }
+#endif
+
+ return dram_size;
+}
+
+
+#if defined(CFG_DRAM_TEST)
+int testdram (void)
+{
+ uint *pstart = (uint *) CFG_MEMTEST_START;
+ uint *pend = (uint *) CFG_MEMTEST_END;
+ uint *p;
+
+ printf("SDRAM test phase 1:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0xaaaaaaaa;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0xaaaaaaaa) {
+ printf ("SDRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf("SDRAM test phase 2:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0x55555555;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0x55555555) {
+ printf ("SDRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf("SDRAM test passed.\n");
+ return 0;
+}
+#endif
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ * fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+long int fixed_sdram (void)
+{
+ #ifndef CFG_RAMBOOT
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+
+ ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
+ ddr->cs0_config = CFG_DDR_CS0_CONFIG;
+ ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
+ ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
+ ddr->sdram_mode = CFG_DDR_MODE;
+ ddr->sdram_interval = CFG_DDR_INTERVAL;
+ #if defined (CONFIG_DDR_ECC)
+ ddr->err_disable = 0x0000000D;
+ ddr->err_sbe = 0x00ff0000;
+ #endif
+ asm("sync;isync;msync");
+ udelay(500);
+ #if defined (CONFIG_DDR_ECC)
+ /* Enable ECC checking */
+ ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
+ #else
+ ddr->sdram_cfg = CFG_DDR_CONTROL;
+ #endif
+ asm("sync; isync; msync");
+ udelay(500);
+ #endif
+ return ( CFG_SDRAM_SIZE * 1024 * 1024);
+}
+#endif /* !defined(CONFIG_SPD_EEPROM) */
diff --git a/board/mpc8560ads/u-boot.lds b/board/mpc8560ads/u-boot.lds
new file mode 100644
index 0000000..4c6c7db
--- /dev/null
+++ b/board/mpc8560ads/u-boot.lds
@@ -0,0 +1,152 @@
+/*
+ * (C) Copyright 2002,2003,Motorola,Inc.
+ * Xianghua Xiao, X.Xiao@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ .bootpg 0xFFFFF000 :
+ {
+ cpu/mpc85xx/start.o (.bootpg)
+ board/mpc8560ads/init.o (.bootpg)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/mpc85xx/start.o (.text)
+ board/mpc8560ads/init.o (.text)
+ cpu/mpc85xx/commproc.o (.text)
+ cpu/mpc85xx/traps.o (.text)
+ cpu/mpc85xx/interrupts.o (.text)
+ cpu/mpc85xx/serial_scc.o (.text)
+ cpu/mpc85xx/ether_fcc.o (.text)
+ cpu/mpc85xx/cpu_init.o (.text)
+ cpu/mpc85xx/cpu.o (.text)
+ cpu/mpc85xx/tsec.o (.text)
+ cpu/mpc85xx/speed.o (.text)
+ cpu/mpc85xx/i2c.o (.text)
+ cpu/mpc85xx/spd_sdram.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_ppc/extable.o (.text)
+ lib_generic/zlib.o (.text)
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/mpl/common/flash.c b/board/mpl/common/flash.c
index 98cfb0d..e56e307 100644
--- a/board/mpl/common/flash.c
+++ b/board/mpl/common/flash.c
@@ -86,14 +86,14 @@
* The first thing we do is to map the Flash CS to the Flash area and
* the MPS CS to the MPS area. Since the flash size is unknown at this
* point, we use the max flash size and the lowest flash address as base.
- *
+ *
* After flash detection we adjust the size of the CS area accordingly.
* The board_init_r will fill in wrong values in the board init structure,
* but this will be fixed in the misc_init_r routine:
* bd->bi_flashstart=0-flash_info[0].size
* bd->bi_flashsize=flash_info[0].size-CFG_MONITOR_LEN
* bd->bi_flashoffset=0
- *
+ *
*/
int get_boot_mode(void)
{
@@ -152,7 +152,6 @@
}
-
unsigned long flash_init (void)
{
unsigned long size_b0, size_b1,flashcr, size_reg;
@@ -207,7 +206,7 @@
case 32: i=5; break; /* = 32MB */
case 64: i=6; break; /* = 64MB */
case 128: i=7; break; /*= 128MB */
- default:
+ default:
printf("\n #### ERROR, wrong size %ld MByte reset board #####\n",size_reg);
while(1);
}
@@ -345,7 +344,7 @@
/*-----------------------------------------------------------------------
-
+
*/
/*
diff --git a/board/mpl/vcma9/cmd_vcma9.c b/board/mpl/vcma9/cmd_vcma9.c
index 3b04535..8df642d 100644
--- a/board/mpl/vcma9/cmd_vcma9.c
+++ b/board/mpl/vcma9/cmd_vcma9.c
@@ -178,4 +178,3 @@
"vcma9 - VCMA9 specific commands\n",
"flash mem [SrcAddr]\n - updates U-Boot with image in memory\n"
);
-
diff --git a/board/mpl/vcma9/memsetup.S b/board/mpl/vcma9/memsetup.S
index ab65901..98aec3d 100644
--- a/board/mpl/vcma9/memsetup.S
+++ b/board/mpl/vcma9/memsetup.S
@@ -153,14 +153,14 @@
ldrb r3, [r2, #SDRAM_REG-PLD_BASE]
mov r4, #SDRAMDATA1_END-SDRAMDATA
/* calculate start and end point */
- mla r0, r3, r4, r0
+ mla r0, r3, r4, r0
add r2, r0, r4
0:
ldr r3, [r0], #4
str r3, [r1], #4
cmp r2, r0
bne 0b
-
+
/* everything is fine now */
mov pc, lr
@@ -194,7 +194,7 @@
.word 0x32 + BURST_EN
.word 0x30
.word 0x30
-
+
/* 2Mx8x4 (not implemented yet) */
.word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
.word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
@@ -202,7 +202,7 @@
.word 0x32 + BURST_EN
.word 0x30
.word 0x30
-
+
/* 4Mx8x2 (not implemented yet) */
.word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
.word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
diff --git a/board/mpl/vcma9/vcma9.c b/board/mpl/vcma9/vcma9.c
index cdf6163..4664488 100644
--- a/board/mpl/vcma9/vcma9.c
+++ b/board/mpl/vcma9/vcma9.c
@@ -190,21 +190,21 @@
static u8 Get_PLD_ID(void)
{
VCMA9_PLD * const pld = VCMA9_GetBase_PLD();
-
+
return(pld->ID);
}
static u8 Get_PLD_BOARD(void)
{
VCMA9_PLD * const pld = VCMA9_GetBase_PLD();
-
+
return(pld->BOARD);
}
static u8 Get_PLD_SDRAM(void)
{
VCMA9_PLD * const pld = VCMA9_GetBase_PLD();
-
+
return(pld->SDRAM);
}
@@ -253,7 +253,7 @@
case 2: return 8 * (1024*1024);
case 3: return 8 * (1024*1024);
default: return 0;
- }
+ }
}
static const char * Get_SDRAM_ChipGeom(void)
{
@@ -339,10 +339,10 @@
* Print VCMA9 Info
************************************************************************/
void print_vcma9_info(void)
-{
+{
unsigned char s[50];
int i;
-
+
if ((i = getenv_r("serial#", s, 32)) < 0) {
puts ("### No HW ID - assuming VCMA9");
printf("i %d", i*24);
diff --git a/board/omap1610inn/flash.c b/board/omap1610inn/flash.c
index 0108545..e7d6515 100644
--- a/board/omap1610inn/flash.c
+++ b/board/omap1610inn/flash.c
@@ -54,7 +54,6 @@
#define mb() __asm__ __volatile__ ("" : : : "memory")
-
/* Flash Organization Structure */
typedef struct OrgDef {
unsigned int sector_number;
@@ -240,8 +239,6 @@
}
-
-
/* unprotects a sector for write and erase
* on some intel parts, this unprotects the entire chip, but it
* wont hurt to call this additional times per sector...
@@ -298,8 +295,6 @@
}
-
-
start = get_timer (0);
last = start;
@@ -326,7 +321,7 @@
while (((status =
*addr) & (FPW) 0x00800080) !=
(FPW) 0x00800080) {
- if (get_timer_masked () >
+ if (get_timer_masked () >
CFG_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
/* suspend erase */
diff --git a/board/omap1610inn/platform.S b/board/omap1610inn/platform.S
index 9e3fc4f..cad152b 100644
--- a/board/omap1610inn/platform.S
+++ b/board/omap1610inn/platform.S
@@ -132,8 +132,6 @@
bne watch2Wait
-
-
/* Set memory timings corresponding to the new clock speed */
/* Check execution location to determine current execution location
@@ -275,7 +273,7 @@
REG_ARM_IDLECT3: /* 16 bits */
.word 0xfffece24
REG_ARM_IDLECT2: /* 16 bits */
- .word 0xfffece08
+ .word 0xfffece08
REG_ARM_IDLECT1: /* 16 bits */
.word 0xfffece04
@@ -293,7 +291,7 @@
.word 0xfffeb048
/* watchdog write pending */
REG_WWPSDOG:
- .word 0xfffeb034
+ .word 0xfffeb034
WSPRDOG_VAL1:
.word 0x0000aaaa
@@ -342,7 +340,7 @@
/* 96 MHz Samsung Mobile DDR */
SDRAM_CONFIG_VAL:
- .word 0x001200f4
+ .word 0x001200f4
DLL_LRD_CONTROL_VAL:
.word 0x00800002
diff --git a/board/omap1610inn/u-boot.lds b/board/omap1610inn/u-boot.lds
index 0a46054..cab0080 100644
--- a/board/omap1610inn/u-boot.lds
+++ b/board/omap1610inn/u-boot.lds
@@ -39,11 +39,11 @@
.data : { *(.data) }
. = ALIGN(4);
.got : { *(.got) }
-
+
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
-
+
armboot_end_data = .;
. = ALIGN(4);
.bss : { *(.bss) }
diff --git a/board/sacsng/sacsng.c b/board/sacsng/sacsng.c
index 60563d4..e50b747 100644
--- a/board/sacsng/sacsng.c
+++ b/board/sacsng/sacsng.c
@@ -533,11 +533,11 @@
setenv("Daq128xSampling", "1");
}
- /*
- * Display the ADC/DAC clocking information
+ /*
+ * Display the ADC/DAC clocking information
*/
if (!quiet) {
- Daq_Display_Clocks();
+ Daq_Display_Clocks();
}
/*
@@ -572,9 +572,9 @@
* 3) Write the I2C address to register 6
* 4) Enable address matching by setting the MSB in register 7
*/
-
+
if (!quiet) {
- printf("Initializing the ADC...\n");
+ printf("Initializing the ADC...\n");
}
udelay(ADC_INITIAL_DELAY); /* 10uSec per uF of VREF cap */
@@ -720,7 +720,7 @@
I2C_TRISTATE;
if (!quiet) {
- printf("\n");
+ printf("\n");
}
#ifdef CONFIG_ETHER_LOOPBACK_TEST
@@ -795,14 +795,14 @@
if(status > 0) {
last_boot_progress = status;
} else {
- /*
+ /*
* If a specific failure code is given, flash this code
* else just use the last success code we've seen
*/
if(status < -1)
last_boot_progress = -status;
-
- /*
+
+ /*
* Flash this code 5 times
*/
for(j=0; j<5; j++) {
@@ -813,15 +813,15 @@
status_led_set(STATUS_LED_RED, STATUS_LED_ON);
flash_code(last_boot_progress, 5, 3);
- /*
- * Delay 5 seconds between repetitions,
- * with the fault LED blinking
+ /*
+ * Delay 5 seconds between repetitions,
+ * with the fault LED blinking
*/
for(i=0; i<5; i++) {
- status_led_set(STATUS_LED_RED, STATUS_LED_OFF);
- udelay(500000);
- status_led_set(STATUS_LED_RED, STATUS_LED_ON);
- udelay(500000);
+ status_led_set(STATUS_LED_RED, STATUS_LED_OFF);
+ udelay(500000);
+ status_led_set(STATUS_LED_RED, STATUS_LED_ON);
+ udelay(500000);
}
}
diff --git a/board/sl8245/sl8245.c b/board/sl8245/sl8245.c
index 3f81f17..d5c1f34 100644
--- a/board/sl8245/sl8245.c
+++ b/board/sl8245/sl8245.c
@@ -92,4 +92,3 @@
{
pci_mpc824x_init(&hose);
}
-
diff --git a/board/tqm8xx/tqm8xx.c b/board/tqm8xx/tqm8xx.c
index f9b04f8..53f1f2a 100644
--- a/board/tqm8xx/tqm8xx.c
+++ b/board/tqm8xx/tqm8xx.c
@@ -368,8 +368,8 @@
memctl->memc_or5 = CFG_OR5_ISP1362;
memctl->memc_br5 = CFG_BR5_ISP1362;
#endif /* CONFIG_ISP1362_USB */
-
-
+
+
return (size_b0 + size_b1);
}
diff --git a/board/trab/memsetup.S b/board/trab/memsetup.S
index f59b0ac..0273b94 100644
--- a/board/trab/memsetup.S
+++ b/board/trab/memsetup.S
@@ -48,8 +48,8 @@
#define BWSCON 0x14000000
/* Bank0 */
-#define B0_Tacs 0x0 /* 0 clk */
-#define B0_Tcos 0x0 /* 0 clk */
+#define B0_Tacs 0x3 /* 4 clk */
+#define B0_Tcos 0x3 /* 4 clk */
#define B0_Tacc 0x7 /* 14 clk */
#define B0_Tcoh 0x0 /* 0 clk */
#define B0_Tah 0x0 /* 0 clk */
diff --git a/board/trab/trab_fkt.c b/board/trab/trab_fkt.c
index 5613281..4769f27 100644
--- a/board/trab/trab_fkt.c
+++ b/board/trab/trab_fkt.c
@@ -885,7 +885,6 @@
}
-
int do_touch (char **argv)
{
int x, y;
@@ -1039,7 +1038,6 @@
}
-
int do_rs485 (char **argv)
{
int timeout;
diff --git a/board/trab/tsc2000.c b/board/trab/tsc2000.c
index ad11860..df2d87f 100644
--- a/board/trab/tsc2000.c
+++ b/board/trab/tsc2000.c
@@ -38,7 +38,7 @@
int i;
/* Configure I/O ports. */
- gpio->PDCON = (gpio->PDCON & 0xF3FFFF) | 0x040000;
+ gpio->PDCON = (gpio->PDCON & 0xF3FFFF) | 0x040000;
gpio->PGCON = (gpio->PGCON & 0x0F3FFF) | 0x008000;
gpio->PGCON = (gpio->PGCON & 0x0CFFFF) | 0x020000;
gpio->PGCON = (gpio->PGCON & 0x03FFFF) | 0x080000;
@@ -48,7 +48,7 @@
spi->ch[0].SPPRE = 0x1F; /* Baud-rate ca. 514kHz */
spi->ch[0].SPPIN = 0x01; /* SPI-MOSI holds Level after last bit */
spi->ch[0].SPCON = 0x1A; /* Polling, Prescaler, Master, CPOL=0,
- CPHA=1 */
+ CPHA=1 */
/* Dummy byte ensures clock to be low. */
for (i = 0; i < 10; i++) {
@@ -73,7 +73,7 @@
SET_CS_TOUCH();
command = reg;
- spi->ch[0].SPTDAT = (command & 0xFF00) >> 8;
+ spi->ch[0].SPTDAT = (command & 0xFF00) >> 8;
spi_wait_transmit_done();
spi->ch[0].SPTDAT = (command & 0x00FF);
spi_wait_transmit_done();
@@ -94,12 +94,12 @@
SET_CS_TOUCH();
command = 0x8000 | reg;
- spi->ch[0].SPTDAT = (command & 0xFF00) >> 8;
+ spi->ch[0].SPTDAT = (command & 0xFF00) >> 8;
spi_wait_transmit_done();
spi->ch[0].SPTDAT = (command & 0x00FF);
spi_wait_transmit_done();
- spi->ch[0].SPTDAT = 0xFF;
+ spi->ch[0].SPTDAT = 0xFF;
spi_wait_transmit_done();
data = spi->ch[0].SPRDAT;
spi->ch[0].SPTDAT = 0xFF;
@@ -112,7 +112,7 @@
void tsc2000_set_mux (unsigned int channel)
{
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
CLR_MUX1_ENABLE; CLR_MUX2_ENABLE;
CLR_MUX3_ENABLE; CLR_MUX4_ENABLE;
@@ -189,7 +189,7 @@
void tsc2000_set_range (unsigned int range)
{
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
switch (range) {
case 1:
@@ -216,8 +216,8 @@
udelay(3 * TSC2000_DELAY_BASE);
tsc2000_write(TSC2000_REG_ADC, 0x2036);
- adc_wait_conversion_done ();
- res = tsc2000_read(TSC2000_REG_AUX1);
+ adc_wait_conversion_done ();
+ res = tsc2000_read(TSC2000_REG_AUX1);
return res;
}
@@ -225,36 +225,36 @@
s32 tsc2000_contact_temp (void)
{
long adc_pt1000, offset;
- long u_pt1000;
+ long u_pt1000;
long contact_temp;
- tsc2000_reg_init ();
+ tsc2000_reg_init ();
tsc2000_set_range (3);
- adc_pt1000 = tsc2000_read_channel (14);
- debug ("read channel 14 (pt1000 adc value): %ld\n", adc_pt1000);
+ adc_pt1000 = tsc2000_read_channel (14);
+ debug ("read channel 14 (pt1000 adc value): %ld\n", adc_pt1000);
- offset = tsc2000_read_channel (15);
- debug ("read channel 15 (offset): %ld\n", offset);
+ offset = tsc2000_read_channel (15);
+ debug ("read channel 15 (offset): %ld\n", offset);
- /*
- * Formula for calculating voltage drop on PT1000 resistor: u_pt1000 =
- * x_range3 * (adc_raw - offset) / 10. Formula to calculate x_range3:
- * x_range3 = (2500 * (1000000 + err_vref + err_amp3)) / (4095*6). The
- * error correction Values err_vref and err_amp3 are assumed as 0 in
- * u-boot, because this could cause only a very small error (< 1%).
- */
- u_pt1000 = (101750 * (adc_pt1000 - offset)) / 10;
- debug ("u_pt1000: %ld\n", u_pt1000);
+ /*
+ * Formula for calculating voltage drop on PT1000 resistor: u_pt1000 =
+ * x_range3 * (adc_raw - offset) / 10. Formula to calculate x_range3:
+ * x_range3 = (2500 * (1000000 + err_vref + err_amp3)) / (4095*6). The
+ * error correction Values err_vref and err_amp3 are assumed as 0 in
+ * u-boot, because this could cause only a very small error (< 1%).
+ */
+ u_pt1000 = (101750 * (adc_pt1000 - offset)) / 10;
+ debug ("u_pt1000: %ld\n", u_pt1000);
- if (tsc2000_interpolate(u_pt1000, Pt1000_temp_table,
- &contact_temp) == -1) {
- printf ("%s: error interpolating PT1000 vlaue\n",
- __FUNCTION__);
- return (-1000);
- }
- debug ("contact_temp: %ld\n", contact_temp);
+ if (tsc2000_interpolate(u_pt1000, Pt1000_temp_table,
+ &contact_temp) == -1) {
+ printf ("%s: error interpolating PT1000 vlaue\n",
+ __FUNCTION__);
+ return (-1000);
+ }
+ debug ("contact_temp: %ld\n", contact_temp);
return contact_temp;
}
@@ -262,7 +262,7 @@
void tsc2000_reg_init (void)
{
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
tsc2000_write(TSC2000_REG_ADC, 0x2036);
tsc2000_write(TSC2000_REG_REF, 0x0011);
@@ -315,5 +315,5 @@
void adc_wait_conversion_done(void)
{
- while (!(tsc2000_read(TSC2000_REG_ADC) & (1 << 14)));
+ while (!(tsc2000_read(TSC2000_REG_ADC) & (1 << 14)));
}
diff --git a/board/trab/tsc2000.h b/board/trab/tsc2000.h
index e6efe18..aac9c0c 100644
--- a/board/trab/tsc2000.h
+++ b/board/trab/tsc2000.h
@@ -112,7 +112,7 @@
#define TSC2000_NO_SENSOR -0x10000
#define ERROR_BATTERY 220 /* must be adjusted, if R68 is changed on
- * TRAB */
+ * TRAB */
void tsc2000_write(unsigned short, unsigned short);
unsigned short tsc2000_read (unsigned short);