include/configs/CANBT.h - platform/external/u-boot - Gitiles

 /*
  * (C) Copyright 2001
  * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

 /*
  * board/config.h - configuration options, board specific
  */

 #ifndef __CONFIG_H
 #define __CONFIG_H

 /*
  * High Level Configuration Options
  * (easy to change)
  */

 #define CONFIG_405CR		1	/* This is a PPC405CR CPU	*/
 #define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
 #define CONFIG_CANBT		1	/* ...on a CANBT board		*/

 #define	CONFIG_SYS_TEXT_BASE	0xFFFC0000

 #define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/

 #define CONFIG_SYS_CLK_FREQ	25000000 /* external frequency to pll	*/

 #define CONFIG_BAUDRATE		115200
 #define CONFIG_BOOTDELAY	1	/* autoboot after 1 seconds	*/

 #undef	CONFIG_BOOTARGS
 #define CONFIG_BOOTCOMMAND						\
 	"setenv bootargs root=/dev/ram rw console=ttyS0,115200; "	\
 	"bootm ffe00000 ffe80000"

 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

 #undef	CONFIG_PCI_PNP			/* no pci plug-and-play		*/

 #define CONFIG_PHY_ADDR		0	/* PHY address			*/


 /*
  * BOOTP options
  */
 #define CONFIG_BOOTP_BOOTFILESIZE
 #define CONFIG_BOOTP_BOOTPATH
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME


 /*
  * Command line configuration.
  */
 #include <config_cmd_default.h>

 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_EEPROM

 #undef CONFIG_CMD_NET
 #undef CONFIG_CMD_NFS

 #undef CONFIG_WATCHDOG			/* watchdog disabled		*/

 #define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/

 /*
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
 #define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
 #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 #define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

 #define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/

 #define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
 #define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

 #define CONFIG_CONS_INDEX	1	/* Use UART0			*/
 #define CONFIG_SYS_NS16550
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	1
 #define CONFIG_SYS_NS16550_CLK		get_serial_clock()

 #define CONFIG_SYS_EXT_SERIAL_CLOCK	14745600 /* use external serial clock	*/

 /* The following table includes the supported baudrates */
 #define CONFIG_SYS_BAUDRATE_TABLE	\
 	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 	 57600, 115200, 230400, 460800, 921600 }

 #define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
 #define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */

 #define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */

 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */

 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
 #define CONFIG_SYS_SDRAM_BASE		0x00000000
 #define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_MONITOR_BASE
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_MONITOR_LEN		(~(CONFIG_SYS_TEXT_BASE) + 1)
 #define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/

 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
 #define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
 #define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
 #define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/

 #define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

 #define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
 #define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
 #define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
 /*
  * The following defines are added for buggy IOP480 byte interface.
  * All other boards should use the standard values (CPCI405 etc.)
  */
 #define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
 #define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
 #define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/

 #define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */

 #if 0 /* Use FLASH for environment variables */

 #define CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_OFFSET		0x00010000	/* Offset of Environment Sector */
 #define CONFIG_ENV_SIZE		0x1000	/* Total Size of Environment Sector	*/

 #define CONFIG_ENV_SECT_SIZE	0x10000 /* see README - env sector total size	*/

 #else /* Use EEPROM for environment variables */

 #define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
 #define CONFIG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
 #define CONFIG_ENV_SIZE		0x400	/* 1024 bytes may be used for env vars */
 				   /* total size of a CAT24WC08 is 1024 bytes */
 #endif

 /*-----------------------------------------------------------------------
  * I2C EEPROM (CAT24WC08) for environment
  */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_PPC4XX
 #define CONFIG_SYS_I2C_PPC4XX_CH0
 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F

 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08	*/
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* bytes of address	*/
 /* mask of address bits that overflow into the "EEPROM chip address"	*/
 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07

 /*
  * Init Memory Controller:
  *
  * BR0/1 and OR0/1 (FLASH)
  */

 #define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/
 #define FLASH_BASE1_PRELIM	0		/* FLASH bank #1	*/

 /*-----------------------------------------------------------------------
  * External Bus Controller (EBC) Setup
  */

 /* Memory Bank 0 (Flash Bank 0) initialization					*/
 #define CONFIG_SYS_EBC_PB0AP		0x92015480
 #define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */

 /* Memory Bank 1 (CAN/USB) initialization					*/
 #define CONFIG_SYS_EBC_PB1AP		0x010053C0  /* enable Ready, BEM=1		*/
 #define CONFIG_SYS_EBC_PB1CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/

 /* Memory Bank 2 (Misc-IO/LEDs) initialization					*/
 #define CONFIG_SYS_EBC_PB2AP		0x000004c0  /* no Ready, BEM=1			*/
 #define CONFIG_SYS_EBC_PB2CR		0xF0118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit	*/

 /* Memory Bank 3 (CAN Features) initialization					*/
 #define CONFIG_SYS_EBC_PB3AP		0x80000040  /* no Ready, BEM=1			*/
 #define CONFIG_SYS_EBC_PB3CR		0xF021C000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=32bit */

 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in RAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	0x00ef0000 /* inside of SDRAM			*/
 #define CONFIG_SYS_INIT_RAM_SIZE	0x0f00	/* Size of used area in RAM	       */
 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

 #endif	/* __CONFIG_H */
	/*
	* (C) Copyright 2001
	* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
	*
	* SPDX-License-Identifier: GPL-2.0+
	*/

	/*
	* board/config.h - configuration options, board specific
	*/

	#ifndef __CONFIG_H
	#define __CONFIG_H

	/*
	* High Level Configuration Options
	* (easy to change)
	*/

	#define CONFIG_405CR 1 /* This is a PPC405CR CPU */
	#define CONFIG_4xx 1 /* ...member of PPC4xx family */
	#define CONFIG_CANBT 1 /* ...on a CANBT board */

	#define CONFIG_SYS_TEXT_BASE 0xFFFC0000

	#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */

	#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */

	#define CONFIG_BAUDRATE 115200
	#define CONFIG_BOOTDELAY 1 /* autoboot after 1 seconds */

	#undef CONFIG_BOOTARGS
	#define CONFIG_BOOTCOMMAND \
	"setenv bootargs root=/dev/ram rw console=ttyS0,115200; " \
	"bootm ffe00000 ffe80000"

	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */

	#undef CONFIG_PCI_PNP /* no pci plug-and-play */

	#define CONFIG_PHY_ADDR 0 /* PHY address */


	/*
	* BOOTP options
	*/
	#define CONFIG_BOOTP_BOOTFILESIZE
	#define CONFIG_BOOTP_BOOTPATH
	#define CONFIG_BOOTP_GATEWAY
	#define CONFIG_BOOTP_HOSTNAME


	/*
	* Command line configuration.
	*/
	#include <config_cmd_default.h>

	#define CONFIG_CMD_IRQ
	#define CONFIG_CMD_EEPROM

	#undef CONFIG_CMD_NET
	#undef CONFIG_CMD_NFS

	#undef CONFIG_WATCHDOG /* watchdog disabled */

	#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */

	/*
	* Miscellaneous configurable options
	*/
	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
	#if defined(CONFIG_CMD_KGDB)
	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
	#else
	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	#endif
	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */

	#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/

	#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
	#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */

	#define CONFIG_CONS_INDEX 1 /* Use UART0 */
	#define CONFIG_SYS_NS16550
	#define CONFIG_SYS_NS16550_SERIAL
	#define CONFIG_SYS_NS16550_REG_SIZE 1
	#define CONFIG_SYS_NS16550_CLK get_serial_clock()

	#define CONFIG_SYS_EXT_SERIAL_CLOCK 14745600 /* use external serial clock */

	/* The following table includes the supported baudrates */
	#define CONFIG_SYS_BAUDRATE_TABLE \
	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
	57600, 115200, 230400, 460800, 921600 }

	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
	#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */

	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */

	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */

	/*-----------------------------------------------------------------------
	* Start addresses for the final memory configuration
	* (Set up by the startup code)
	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
	*/
	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE
	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
	#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1)
	#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */

	/*
	* For booting Linux, the board info and command line data
	* have to be in the first 8 MB of memory, since this is
	* the maximum mapped by the Linux kernel during initialization.
	*/
	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	/*-----------------------------------------------------------------------
	* FLASH organization
	*/
	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */

	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */

	#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
	#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
	#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
	/*
	* The following defines are added for buggy IOP480 byte interface.
	* All other boards should use the standard values (CPCI405 etc.)
	*/
	#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
	#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
	#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */

	#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */

	#if 0 /* Use FLASH for environment variables */

	#define CONFIG_ENV_IS_IN_FLASH 1
	#define CONFIG_ENV_OFFSET 0x00010000 /* Offset of Environment Sector */
	#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */

	#define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */

	#else /* Use EEPROM for environment variables */

	#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
	#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
	#define CONFIG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars */
	/* total size of a CAT24WC08 is 1024 bytes */
	#endif

	/*-----------------------------------------------------------------------
	* I2C EEPROM (CAT24WC08) for environment
	*/
	#define CONFIG_SYS_I2C
	#define CONFIG_SYS_I2C_PPC4XX
	#define CONFIG_SYS_I2C_PPC4XX_CH0
	#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
	#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F

	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
	/* mask of address bits that overflow into the "EEPROM chip address" */
	#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07

	/*
	* Init Memory Controller:
	*
	* BR0/1 and OR0/1 (FLASH)
	*/

	#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
	#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */

	/*-----------------------------------------------------------------------
	* External Bus Controller (EBC) Setup
	*/

	/* Memory Bank 0 (Flash Bank 0) initialization */
	#define CONFIG_SYS_EBC_PB0AP 0x92015480
	#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */

	/* Memory Bank 1 (CAN/USB) initialization */
	#define CONFIG_SYS_EBC_PB1AP 0x010053C0 /* enable Ready, BEM=1 */
	#define CONFIG_SYS_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */

	/* Memory Bank 2 (Misc-IO/LEDs) initialization */
	#define CONFIG_SYS_EBC_PB2AP 0x000004c0 /* no Ready, BEM=1 */
	#define CONFIG_SYS_EBC_PB2CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */

	/* Memory Bank 3 (CAN Features) initialization */
	#define CONFIG_SYS_EBC_PB3AP 0x80000040 /* no Ready, BEM=1 */
	#define CONFIG_SYS_EBC_PB3CR 0xF021C000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=32bit */

	/*-----------------------------------------------------------------------
	* Definitions for initial stack pointer and data area (in RAM)
	*/
	#define CONFIG_SYS_INIT_RAM_ADDR 0x00ef0000 /* inside of SDRAM */
	#define CONFIG_SYS_INIT_RAM_SIZE 0x0f00 /* Size of used area in RAM */
	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET

	#endif /* __CONFIG_H */