| if RAM || SPL_RAM |
| |
| config ASPEED_DDR4_DUALX8 |
| bool "Enable Dual X8 DDR4 die" |
| depends on DM && OF_CONTROL && ARCH_ASPEED |
| help |
| Say Y if dual X8 DDR4 die is used on the board. The aspeed ddr sdram |
| controller needs to know if the memory chip mounted on the board is dual |
| x8 die or not. Or it may get the wrong size of the memory space. |
| |
| if ASPEED_AST2600 |
| |
| choice |
| prompt "DDR4 target date rate" |
| default ASPEED_DDR4_1600 |
| |
| config ASPEED_DDR4_400 |
| bool "DDR4 targets at 400Mbps" |
| depends on DM && OF_CONTROL && ARCH_ASPEED |
| help |
| select DDR4 target data rate at 400M |
| |
| config ASPEED_DDR4_800 |
| bool "DDR4 targets at 800Mbps" |
| depends on DM && OF_CONTROL && ARCH_ASPEED |
| help |
| select DDR4 target data rate at 800M |
| |
| config ASPEED_DDR4_1333 |
| bool "DDR4 targets at 1333Mbps" |
| depends on DM && OF_CONTROL && ARCH_ASPEED |
| help |
| select DDR4 target data rate at 1333M |
| |
| config ASPEED_DDR4_1600 |
| bool "DDR4 targets at 1600Mbps" |
| depends on DM && OF_CONTROL && ARCH_ASPEED |
| help |
| select DDR4 target data rate at 1600M |
| endchoice |
| |
| config ASPEED_BYPASS_SELFTEST |
| bool "bypass self test during DRAM initialization" |
| help |
| Say Y here to bypass DRAM self test to speed up the boot time |
| |
| config ASPEED_ECC |
| bool "aspeed SDRAM error correcting code" |
| depends on DM && OF_CONTROL && ARCH_ASPEED |
| help |
| enable SDRAM ECC function |
| |
| if ASPEED_ECC |
| config ASPEED_ECC_SIZE |
| int "ECC size: 0=driver auto-caluated" |
| depends on ASPEED_ECC |
| default 0 |
| help |
| SDRAM size with the error correcting code enabled. The unit is |
| in Megabytes. Noted that only the 8/9 of the configured size |
| can be used by the system. The remaining 1/9 will be used by |
| the ECC engine. If the size is set to 0, the sdram driver will |
| calculate the SDRAM size and set the whole range be ECC enabled. |
| endif # end of ASPEED_ECC |
| endif # end of ASPEED_AST2600 |
| endif # end of RAM || SPL_RAM |