include/configs/mcc200.h - platform/external/u-boot - Gitiles

 /*
  * (C) Copyright 2006
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */

 #ifndef __CONFIG_H
 #define __CONFIG_H

 /*
  * High Level Configuration Options
  * (easy to change)
  */

 #define CONFIG_MPC5200
 #define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU		*/
 #define CONFIG_MCC200		1	/* ... on MCC200 board			*/

 #define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33MHz		*/

 #define CONFIG_MISC_INIT_R

 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH 	*/
 #define BOOTFLAG_WARM		0x02	/* Software reboot	     		*/

 #define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs 			*/
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 #  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value 	*/
 #endif

 /*
  * Serial console configuration
  */
 #define CONFIG_PSC_CONSOLE	1	/* console is on PSC1			*/
 #define CONFIG_BAUDRATE		115200
 #define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

 #define CONFIG_MII		1

 #define CONFIG_DOS_PARTITION

 /* USB */
 #define CONFIG_USB_OHCI
 #define ADD_USB_CMD             CFG_CMD_USB | CFG_CMD_FAT
 #define CONFIG_USB_STORAGE

 /*
  * Supported commands
  */
 #define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
 				ADD_USB_CMD	| \
 				CFG_CMD_BEDBUG	| \
 				CFG_CMD_DATE	| \
 				CFG_CMD_DHCP	| \
 				CFG_CMD_EEPROM	| \
 				CFG_CMD_FAT	| \
 				CFG_CMD_I2C	| \
 				CFG_CMD_NFS	| \
 				CFG_CMD_SNTP	)

 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>

 /*
  * Autobooting
  */
 #define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */

 #define CONFIG_PREBOOT	"echo;"	\
 	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
 	"echo"

 #undef	CONFIG_BOOTARGS

 #define	CONFIG_EXTRA_ENV_SETTINGS					\
 	"netdev=eth0\0"							\
 	"hostname=mcc200\0"						\
 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
 		"nfsroot=${serverip}:${rootpath}\0"			\
 	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
 	"addip=setenv bootargs ${bootargs} "				\
 		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
 		":${hostname}:${netdev}:off panic=1\0"			\
 	"flash_nfs=run nfsargs addip;"					\
 		"bootm ${kernel_addr}\0"				\
 	"flash_self=run ramargs addip;"					\
 		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
 	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
 	"rootpath=/opt/eldk/ppc_6xx\0"					\
 	"bootfile=/tftpboot/mcc200/uImage\0"				\
 	"baudrate=115200\0"						\
 	"load=tftp 200000 /tftpboot/mcc200/u-boot.bin\0"		\
 	"update=protect off FFF00000 +${filesize};"			\
 		"era FFF00000 +${filesize};"				\
 		"cp.b 200000 FFF00000 ${filesize}\0"		        \
 	"serverip=192.168.1.1\0"					\
 	"ipaddr=192.168.133.144\0"					\
 	"netmask=255.255.0.0\0"						\
 	"unlock=yes\0"							\
 	"ethaddr=00:02:44:7D:73:3B\0"					\
 	""

 #define CONFIG_BOOTCOMMAND	"run flash_self"

 #define CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
 #define CFG_PROMPT_HUSH_PS2	"> "

 /*
  * IPB Bus clocking configuration.
  */
 #define CFG_IPBSPEED_133   		/* define for 133MHz speed */

 /*
  * I2C configuration
  */
 #define CONFIG_HARD_I2C		1	/* I2C with hardware support */
 #define CFG_I2C_MODULE		2	/* Select I2C module #1 or #2 */

 #define CFG_I2C_SPEED		100000 /* 100 kHz */
 #define CFG_I2C_SLAVE		0x7F

 /*
  * EEPROM configuration
  */
 #define CFG_I2C_EEPROM_ADDR		0x58
 #define CFG_I2C_EEPROM_ADDR_LEN		1
 #define CFG_EEPROM_PAGE_WRITE_BITS	4
 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10

 /*
  * RTC configuration
  */
 #define CONFIG_RTC_PCF8563
 #define CFG_I2C_RTC_ADDR		0x51

 /*
  * Flash configuration (8,16 or 32 MB)
  * TEXT base always at 0xFFF00000
  * ENV_ADDR always at  0xFFF40000
  * FLASH_BASE at 0xFC000000 for 64 MB (only 32MB are supported, not enough addr lines!!!)
  *               0xFE000000 for 32 MB
  *               0xFF000000 for 16 MB
  *               0xFF800000 for  8 MB
  */
 #define CFG_FLASH_BASE		0xfc000000
 #define CFG_FLASH_SIZE		0x04000000

 #define CFG_FLASH_CFI				/* The flash is CFI compatible	*/
 #define CFG_FLASH_CFI_DRIVER			/* Use common CFI driver	*/

 #define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }

 #define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
 #define CFG_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/

 #define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
 #define CFG_FLASH_PROTECTION	1	/* hardware flash protection		*/

 #define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
 #define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

 #define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 #define CFG_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash	*/

 #define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/

 #define CFG_ENV_SECT_SIZE	0x40000 	/* size of one complete sector	*/
 #define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
 #define	CFG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/

 /* Address and size of Redundant Environment Sector	*/
 #define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
 #define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)

 #define CONFIG_ENV_OVERWRITE	1	/* allow modification of vendor params */

 /*
  * Memory map
  */
 #define CFG_MBAR		0xf0000000
 #define CFG_SDRAM_BASE		0x00000000
 #define CFG_DEFAULT_MBAR	0x80000000

 /* Use SRAM until RAM will be available */
 #define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
 #define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */


 #define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 #define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 #define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

 #define CFG_MONITOR_BASE    TEXT_BASE
 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 #   define CFG_RAMBOOT		1
 #endif

 #define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
 #define CFG_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()	*/
 #define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

 /*
  * Ethernet configuration
  */
 #define CONFIG_MPC5xxx_FEC	1
 /*
  * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
  */
 /* #define CONFIG_FEC_10MBIT 1 */
 #define CONFIG_PHY_ADDR		1

 /*
  * GPIO configuration
  */
 //###CHD: MSB = 1 -> 64MB: funktioniert nicht: ERRATA - BUG?
 //###CHD: 0x10000004 = 32MB SDRAM
 //###CHD: 0x90000004 = 64MB SDRAM
 #define CFG_GPS_PORT_CONFIG	0x10000004

 /*
  * Miscellaneous configurable options
  */
 #define CFG_LONGHELP			/* undef to save memory	    */
 #define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 #define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
 #define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
 #endif
 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
 #define CFG_MAXARGS		16		/* max number of command args	*/
 #define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/

 #define CFG_MEMTEST_START	0x00100000	/* memtest works on */
 #define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/

 #define CFG_LOAD_ADDR		0x100000	/* default load address */

 #define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */

 /*
  * Various low-level settings
  */
 #define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
 #define CFG_HID0_FINAL		HID0_ICE

 #define CFG_BOOTCS_START	CFG_FLASH_BASE
 #define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
 #define CFG_BOOTCS_CFG		0x0004fb00
 #define CFG_CS0_START		CFG_FLASH_BASE
 #define CFG_CS0_SIZE		CFG_FLASH_SIZE

 #define CFG_CS_BURST		0x00000000
 #define CFG_CS_DEADCYCLE	0x33333333

 #define CFG_RESET_ADDRESS	0xff000000

 /*-----------------------------------------------------------------------
  * USB stuff
  *-----------------------------------------------------------------------
  */
 #define CONFIG_USB_CLOCK	0x0001BBBB
 #define CONFIG_USB_CONFIG	0x00005000

 #endif /* __CONFIG_H */
	/*
	* (C) Copyright 2006
	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	*
	* See file CREDITS for list of people who contributed to this
	* project.
	*
	* This program is free software; you can redistribute it and/or
	* modify it under the terms of the GNU General Public License as
	* published by the Free Software Foundation; either version 2 of
	* the License, or (at your option) any later version.
	*
	* This program is distributed in the hope that it will be useful,
	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	* GNU General Public License for more details.
	*
	* You should have received a copy of the GNU General Public License
	* along with this program; if not, write to the Free Software
	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	* MA 02111-1307 USA
	*/

	#ifndef __CONFIG_H
	#define __CONFIG_H

	/*
	* High Level Configuration Options
	* (easy to change)
	*/

	#define CONFIG_MPC5200
	#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
	#define CONFIG_MCC200 1 /* ... on MCC200 board */

	#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */

	#define CONFIG_MISC_INIT_R

	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	#define BOOTFLAG_WARM 0x02 /* Software reboot */

	#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
	#endif

	/*
	* Serial console configuration
	*/
	#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
	#define CONFIG_BAUDRATE 115200
	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }

	#define CONFIG_MII 1

	#define CONFIG_DOS_PARTITION

	/* USB */
	#define CONFIG_USB_OHCI
	#define ADD_USB_CMD CFG_CMD_USB \| CFG_CMD_FAT
	#define CONFIG_USB_STORAGE

	/*
	* Supported commands
	*/
	#define CONFIG_COMMANDS (CONFIG_CMD_DFL \| \
	ADD_USB_CMD \| \
	CFG_CMD_BEDBUG \| \
	CFG_CMD_DATE \| \
	CFG_CMD_DHCP \| \
	CFG_CMD_EEPROM \| \
	CFG_CMD_FAT \| \
	CFG_CMD_I2C \| \
	CFG_CMD_NFS \| \
	CFG_CMD_SNTP )

	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
	#include <cmd_confdefs.h>

	/*
	* Autobooting
	*/
	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */

	#define CONFIG_PREBOOT "echo;" \
	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
	"echo"

	#undef CONFIG_BOOTARGS

	#define CONFIG_EXTRA_ENV_SETTINGS \
	"netdev=eth0\0" \
	"hostname=mcc200\0" \
	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	"nfsroot=${serverip}:${rootpath}\0" \
	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	"addip=setenv bootargs ${bootargs} " \
	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	":${hostname}:${netdev}:off panic=1\0" \
	"flash_nfs=run nfsargs addip;" \
	"bootm ${kernel_addr}\0" \
	"flash_self=run ramargs addip;" \
	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
	"rootpath=/opt/eldk/ppc_6xx\0" \
	"bootfile=/tftpboot/mcc200/uImage\0" \
	"baudrate=115200\0" \
	"load=tftp 200000 /tftpboot/mcc200/u-boot.bin\0" \
	"update=protect off FFF00000 +${filesize};" \
	"era FFF00000 +${filesize};" \
	"cp.b 200000 FFF00000 ${filesize}\0" \
	"serverip=192.168.1.1\0" \
	"ipaddr=192.168.133.144\0" \
	"netmask=255.255.0.0\0" \
	"unlock=yes\0" \
	"ethaddr=00:02:44:7D:73:3B\0" \
	""

	#define CONFIG_BOOTCOMMAND "run flash_self"

	#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
	#define CFG_PROMPT_HUSH_PS2 "> "

	/*
	* IPB Bus clocking configuration.
	*/
	#define CFG_IPBSPEED_133 /* define for 133MHz speed */

	/*
	* I2C configuration
	*/
	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
	#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */

	#define CFG_I2C_SPEED 100000 /* 100 kHz */
	#define CFG_I2C_SLAVE 0x7F

	/*
	* EEPROM configuration
	*/
	#define CFG_I2C_EEPROM_ADDR 0x58
	#define CFG_I2C_EEPROM_ADDR_LEN 1
	#define CFG_EEPROM_PAGE_WRITE_BITS 4
	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10

	/*
	* RTC configuration
	*/
	#define CONFIG_RTC_PCF8563
	#define CFG_I2C_RTC_ADDR 0x51

	/*
	* Flash configuration (8,16 or 32 MB)
	* TEXT base always at 0xFFF00000
	* ENV_ADDR always at 0xFFF40000
	* FLASH_BASE at 0xFC000000 for 64 MB (only 32MB are supported, not enough addr lines!!!)
	* 0xFE000000 for 32 MB
	* 0xFF000000 for 16 MB
	* 0xFF800000 for 8 MB
	*/
	#define CFG_FLASH_BASE 0xfc000000
	#define CFG_FLASH_SIZE 0x04000000

	#define CFG_FLASH_CFI /* The flash is CFI compatible */
	#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */

	#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }

	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
	#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */

	#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
	#define CFG_FLASH_PROTECTION 1 /* hardware flash protection */

	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */

	#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
	#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */

	#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */

	#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
	#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
	#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */

	/* Address and size of Redundant Environment Sector */
	#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
	#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)

	#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */

	/*
	* Memory map
	*/
	#define CFG_MBAR 0xf0000000
	#define CFG_SDRAM_BASE 0x00000000
	#define CFG_DEFAULT_MBAR 0x80000000

	/* Use SRAM until RAM will be available */
	#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
	#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */


	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET

	#define CFG_MONITOR_BASE TEXT_BASE
	#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
	# define CFG_RAMBOOT 1
	#endif

	#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	#define CFG_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */

	/*
	* Ethernet configuration
	*/
	#define CONFIG_MPC5xxx_FEC 1
	/*
	* Define CONFIG_FEC_10MBIT to force FEC at 10Mb
	*/
	/* #define CONFIG_FEC_10MBIT 1 */
	#define CONFIG_PHY_ADDR 1

	/*
	* GPIO configuration
	*/
	//###CHD: MSB = 1 -> 64MB: funktioniert nicht: ERRATA - BUG?
	//###CHD: 0x10000004 = 32MB SDRAM
	//###CHD: 0x90000004 = 64MB SDRAM
	#define CFG_GPS_PORT_CONFIG 0x10000004

	/*
	* Miscellaneous configurable options
	*/
	#define CFG_LONGHELP /* undef to save memory */
	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	#else
	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	#endif
	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	#define CFG_MAXARGS 16 /* max number of command args */
	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */

	#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
	#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */

	#define CFG_LOAD_ADDR 0x100000 /* default load address */

	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */

	/*
	* Various low-level settings
	*/
	#define CFG_HID0_INIT HID0_ICE \| HID0_ICFI
	#define CFG_HID0_FINAL HID0_ICE

	#define CFG_BOOTCS_START CFG_FLASH_BASE
	#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
	#define CFG_BOOTCS_CFG 0x0004fb00
	#define CFG_CS0_START CFG_FLASH_BASE
	#define CFG_CS0_SIZE CFG_FLASH_SIZE

	#define CFG_CS_BURST 0x00000000
	#define CFG_CS_DEADCYCLE 0x33333333

	#define CFG_RESET_ADDRESS 0xff000000

	/*-----------------------------------------------------------------------
	* USB stuff
	*-----------------------------------------------------------------------
	*/
	#define CONFIG_USB_CLOCK 0x0001BBBB
	#define CONFIG_USB_CONFIG 0x00005000

	#endif /* __CONFIG_H */