| /* SPDX-License-Identifier: GPL-2.0+ */ |
| /* |
| * Copyright 2018 NXP |
| */ |
| |
| #ifndef __IMX8QM_MEK_H |
| #define __IMX8QM_MEK_H |
| |
| #include <linux/sizes.h> |
| #include <linux/stringify.h> |
| #include <asm/arch/imx-regs.h> |
| |
| #define CONFIG_SYS_BOOTM_LEN (64 * SZ_1M) |
| |
| #ifdef CONFIG_SPL_BUILD |
| #define CONFIG_SPL_MAX_SIZE (124 * 1024) |
| #define CONFIG_SYS_MONITOR_LEN (1024 * 1024) |
| |
| #define CONFIG_SPL_STACK 0x013E000 |
| #define CONFIG_SPL_BSS_START_ADDR 0x00128000 |
| #define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */ |
| #define CONFIG_SYS_SPL_MALLOC_START 0x00120000 |
| #define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */ |
| #define CONFIG_SERIAL_LPUART_BASE 0x5a060000 |
| #define CONFIG_MALLOC_F_ADDR 0x00120000 |
| |
| #define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE |
| |
| #define CONFIG_SPL_ABORT_ON_RAW_IMAGE |
| #endif |
| |
| #define CONFIG_SYS_FSL_ESDHC_ADDR 0 |
| #define USDHC1_BASE_ADDR 0x5B010000 |
| #define USDHC2_BASE_ADDR 0x5B020000 |
| |
| #ifdef CONFIG_AHAB_BOOT |
| #define AHAB_ENV "sec_boot=yes\0" |
| #else |
| #define AHAB_ENV "sec_boot=no\0" |
| #endif |
| |
| /* Initial environment variables */ |
| #define CONFIG_EXTRA_ENV_SETTINGS \ |
| AHAB_ENV \ |
| "script=boot.scr\0" \ |
| "image=Image\0" \ |
| "panel=NULL\0" \ |
| "console=ttyLP0,${baudrate} earlycon=lpuart32,0x5a060000,${baudrate}\0" \ |
| "fdt_addr=0x83000000\0" \ |
| "fdt_high=0xffffffffffffffff\0" \ |
| "boot_fdt=try\0" \ |
| "fdt_file=undefined\0" \ |
| "initrd_addr=0x83800000\0" \ |
| "initrd_high=0xffffffffffffffff\0" \ |
| "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ |
| "mmcpart=1\0" \ |
| "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ |
| "mmcautodetect=yes\0" \ |
| "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \ |
| "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ |
| "bootscript=echo Running bootscript from mmc ...; " \ |
| "source\0" \ |
| "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ |
| "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ |
| "boot_os=booti ${loadaddr} - ${fdt_addr};\0" \ |
| "loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file}\0" \ |
| "auth_os=auth_cntr ${cntr_addr}\0" \ |
| "mmcboot=echo Booting from mmc ...; " \ |
| "run mmcargs; " \ |
| "if test ${sec_boot} = yes; then " \ |
| "if run auth_os; then " \ |
| "run boot_os; " \ |
| "else " \ |
| "echo ERR: failed to authenticate; " \ |
| "fi; " \ |
| "else " \ |
| "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ |
| "if run loadfdt; then " \ |
| "run boot_os; " \ |
| "else " \ |
| "echo WARN: Cannot load the DT; " \ |
| "fi; " \ |
| "else " \ |
| "echo wait for boot; " \ |
| "fi;" \ |
| "fi;\0" \ |
| "netargs=setenv bootargs console=${console} " \ |
| "root=/dev/nfs " \ |
| "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ |
| "netboot=echo Booting from net ...; " \ |
| "run netargs; " \ |
| "if test ${ip_dyn} = yes; then " \ |
| "setenv get_cmd dhcp; " \ |
| "else " \ |
| "setenv get_cmd tftp; " \ |
| "fi; " \ |
| "if test ${sec_boot} = yes; then " \ |
| "${get_cmd} ${cntr_addr} ${cntr_file}; " \ |
| "if run auth_os; then " \ |
| "run boot_os; " \ |
| "else " \ |
| "echo ERR: failed to authenticate; " \ |
| "fi; " \ |
| "else " \ |
| "${get_cmd} ${loadaddr} ${image}; " \ |
| "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ |
| "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ |
| "booti ${loadaddr} - ${fdt_addr}; " \ |
| "else " \ |
| "echo WARN: Cannot load the DT; " \ |
| "fi; " \ |
| "else " \ |
| "booti; " \ |
| "fi;" \ |
| "fi;\0" |
| |
| /* Link Definitions */ |
| |
| #define CONFIG_SYS_INIT_SP_ADDR 0x80200000 |
| |
| /* Default environment is in SD */ |
| |
| /* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */ |
| #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ |
| #define CONFIG_SYS_FSL_USDHC_NUM 2 |
| |
| #define CONFIG_SYS_SDRAM_BASE 0x80000000 |
| #define PHYS_SDRAM_1 0x80000000 |
| #define PHYS_SDRAM_2 0x880000000 |
| #define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ |
| #define PHYS_SDRAM_2_SIZE 0x100000000 /* 4 GB */ |
| |
| /* Generic Timer Definitions */ |
| #define COUNTER_FREQUENCY 8000000 /* 8MHz */ |
| |
| #endif /* __IMX8QM_MEK_H */ |