riscv: cache: Implement i/dcache [status, enable, disable]
AndeStar RISC-V(V5) provide mcache_ctl register which
can configure I/D cache as enabled or disabled.
This CSR will be encapsulated by CONFIG_RISCV_NDS.
If you want to configure cache on AndeStar V5
AE350 platform. YOu can enable [*] AndeStar V5 ISA support
by make menuconfig.
This approach also provide the expansion when the
vender specific features are going to join in.
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 0de77a7..3e0af55 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -16,9 +16,15 @@
endchoice
+# board-specific options below
source "board/AndesTech/ax25-ae350/Kconfig"
source "board/emulation/qemu-riscv/Kconfig"
+# platform-specific options below
+source "arch/riscv/cpu/ax25/Kconfig"
+
+# architecture-specific options below
+
choice
prompt "Base ISA"
default ARCH_RV32I