| /* |
| * sama5d4.dtsi - Device Tree Include file for SAMA5D4 family SoC |
| * |
| * Copyright (C) 2014 Atmel, |
| * 2014 Nicolas Ferre <nicolas.ferre@atmel.com> |
| * |
| * This file is dual-licensed: you can use it either under the terms |
| * of the GPL or the X11 license, at your option. Note that this dual |
| * licensing only applies to this file, and not this project as a |
| * whole. |
| * |
| * a) This file is free software; you can redistribute it and/or |
| * modify it under the terms of the GNU General Public License as |
| * published by the Free Software Foundation; either version 2 of the |
| * License, or (at your option) any later version. |
| * |
| * This file is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * Or, alternatively, |
| * |
| * b) Permission is hereby granted, free of charge, to any person |
| * obtaining a copy of this software and associated documentation |
| * files (the "Software"), to deal in the Software without |
| * restriction, including without limitation the rights to use, |
| * copy, modify, merge, publish, distribute, sublicense, and/or |
| * sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following |
| * conditions: |
| * |
| * The above copyright notice and this permission notice shall be |
| * included in all copies or substantial portions of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES |
| * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT |
| * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
| * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| * OTHER DEALINGS IN THE SOFTWARE. |
| */ |
| |
| #include "skeleton.dtsi" |
| #include <dt-bindings/clock/at91.h> |
| #include <dt-bindings/dma/at91.h> |
| #include <dt-bindings/pinctrl/at91.h> |
| #include <dt-bindings/interrupt-controller/irq.h> |
| #include <dt-bindings/gpio/gpio.h> |
| |
| / { |
| model = "Atmel SAMA5D4 family SoC"; |
| compatible = "atmel,sama5d4"; |
| interrupt-parent = <&aic>; |
| |
| aliases { |
| serial0 = &usart3; |
| serial1 = &usart4; |
| serial2 = &usart2; |
| serial3 = &usart0; |
| serial4 = &usart1; |
| serial5 = &uart0; |
| serial6 = &uart1; |
| gpio0 = &pioA; |
| gpio1 = &pioB; |
| gpio2 = &pioC; |
| gpio3 = &pioD; |
| gpio4 = &pioE; |
| pwm0 = &pwm0; |
| ssc0 = &ssc0; |
| ssc1 = &ssc1; |
| tcb0 = &tcb0; |
| tcb1 = &tcb1; |
| i2c0 = &i2c0; |
| i2c1 = &i2c1; |
| i2c2 = &i2c2; |
| }; |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a5"; |
| reg = <0>; |
| next-level-cache = <&L2>; |
| }; |
| }; |
| |
| memory { |
| reg = <0x20000000 0x20000000>; |
| }; |
| |
| clocks { |
| slow_xtal: slow_xtal { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <0>; |
| }; |
| |
| main_xtal: main_xtal { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <0>; |
| }; |
| |
| adc_op_clk: adc_op_clk{ |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <1000000>; |
| }; |
| }; |
| |
| ns_sram: sram@00210000 { |
| compatible = "mmio-sram"; |
| reg = <0x00210000 0x10000>; |
| }; |
| |
| ahb { |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| u-boot,dm-pre-reloc; |
| |
| usb0: gadget@00400000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "atmel,sama5d3-udc"; |
| reg = <0x00400000 0x100000 |
| 0xfc02c000 0x4000>; |
| interrupts = <47 IRQ_TYPE_LEVEL_HIGH 2>; |
| clocks = <&udphs_clk>, <&utmi>; |
| clock-names = "pclk", "hclk"; |
| status = "disabled"; |
| |
| ep0: endpoint@0 { |
| reg = <0>; |
| atmel,fifo-size = <64>; |
| atmel,nb-banks = <1>; |
| }; |
| |
| ep1: endpoint@1 { |
| reg = <1>; |
| atmel,fifo-size = <1024>; |
| atmel,nb-banks = <3>; |
| atmel,can-dma; |
| atmel,can-isoc; |
| }; |
| |
| ep2: endpoint@2 { |
| reg = <2>; |
| atmel,fifo-size = <1024>; |
| atmel,nb-banks = <3>; |
| atmel,can-dma; |
| atmel,can-isoc; |
| }; |
| |
| ep3: endpoint@3 { |
| reg = <3>; |
| atmel,fifo-size = <1024>; |
| atmel,nb-banks = <2>; |
| atmel,can-dma; |
| atmel,can-isoc; |
| }; |
| |
| ep4: endpoint@4 { |
| reg = <4>; |
| atmel,fifo-size = <1024>; |
| atmel,nb-banks = <2>; |
| atmel,can-dma; |
| atmel,can-isoc; |
| }; |
| |
| ep5: endpoint@5 { |
| reg = <5>; |
| atmel,fifo-size = <1024>; |
| atmel,nb-banks = <2>; |
| atmel,can-dma; |
| atmel,can-isoc; |
| }; |
| |
| ep6: endpoint@6 { |
| reg = <6>; |
| atmel,fifo-size = <1024>; |
| atmel,nb-banks = <2>; |
| atmel,can-dma; |
| atmel,can-isoc; |
| }; |
| |
| ep7: endpoint@7 { |
| reg = <7>; |
| atmel,fifo-size = <1024>; |
| atmel,nb-banks = <2>; |
| atmel,can-dma; |
| atmel,can-isoc; |
| }; |
| |
| ep8: endpoint@8 { |
| reg = <8>; |
| atmel,fifo-size = <1024>; |
| atmel,nb-banks = <2>; |
| atmel,can-isoc; |
| }; |
| |
| ep9: endpoint@9 { |
| reg = <9>; |
| atmel,fifo-size = <1024>; |
| atmel,nb-banks = <2>; |
| atmel,can-isoc; |
| }; |
| |
| ep10: endpoint@10 { |
| reg = <10>; |
| atmel,fifo-size = <1024>; |
| atmel,nb-banks = <2>; |
| atmel,can-isoc; |
| }; |
| |
| ep11: endpoint@11 { |
| reg = <11>; |
| atmel,fifo-size = <1024>; |
| atmel,nb-banks = <2>; |
| atmel,can-isoc; |
| }; |
| |
| ep12: endpoint@12 { |
| reg = <12>; |
| atmel,fifo-size = <1024>; |
| atmel,nb-banks = <2>; |
| atmel,can-isoc; |
| }; |
| |
| ep13: endpoint@13 { |
| reg = <13>; |
| atmel,fifo-size = <1024>; |
| atmel,nb-banks = <2>; |
| atmel,can-isoc; |
| }; |
| |
| ep14: endpoint@14 { |
| reg = <14>; |
| atmel,fifo-size = <1024>; |
| atmel,nb-banks = <2>; |
| atmel,can-isoc; |
| }; |
| |
| ep15: endpoint@15 { |
| reg = <15>; |
| atmel,fifo-size = <1024>; |
| atmel,nb-banks = <2>; |
| atmel,can-isoc; |
| }; |
| }; |
| |
| usb1: ohci@00500000 { |
| compatible = "atmel,at91rm9200-ohci", "usb-ohci"; |
| reg = <0x00500000 0x100000>; |
| interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>; |
| clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; |
| clock-names = "ohci_clk", "hclk", "uhpck"; |
| status = "disabled"; |
| }; |
| |
| usb2: ehci@00600000 { |
| compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; |
| reg = <0x00600000 0x100000>; |
| interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>; |
| clocks = <&utmi>, <&uhphs_clk>; |
| clock-names = "usb_clk", "ehci_clk"; |
| status = "disabled"; |
| }; |
| |
| L2: cache-controller@00a00000 { |
| compatible = "arm,pl310-cache"; |
| reg = <0x00a00000 0x1000>; |
| interrupts = <67 IRQ_TYPE_LEVEL_HIGH 4>; |
| cache-unified; |
| cache-level = <2>; |
| }; |
| |
| nand0: nand@80000000 { |
| compatible = "atmel,sama5d4-nand", "atmel,at91rm9200-nand"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| reg = < 0x80000000 0x08000000 /* EBI CS3 */ |
| 0xfc05c070 0x00000490 /* SMC PMECC regs */ |
| 0xfc05c500 0x00000100 /* SMC PMECC Error Location regs */ |
| >; |
| interrupts = <22 IRQ_TYPE_LEVEL_HIGH 6>; |
| atmel,nand-addr-offset = <21>; |
| atmel,nand-cmd-offset = <22>; |
| atmel,nand-has-dma; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_nand>; |
| status = "disabled"; |
| |
| nfc@90000000 { |
| compatible = "atmel,sama5d3-nfc"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| reg = < |
| 0x90000000 0x08000000 /* NFC Command Registers */ |
| 0xfc05c000 0x00000070 /* NFC HSMC regs */ |
| 0x00100000 0x00100000 /* NFC SRAM banks */ |
| >; |
| clocks = <&hsmc_clk>; |
| atmel,write-by-sram; |
| }; |
| }; |
| |
| apb { |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| u-boot,dm-pre-reloc; |
| |
| hlcdc: hlcdc@f0000000 { |
| compatible = "atmel,sama5d4-hlcdc"; |
| reg = <0xf0000000 0x4000>; |
| interrupts = <51 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; |
| clock-names = "periph_clk","sys_clk", "slow_clk"; |
| status = "disabled"; |
| |
| hlcdc-display-controller { |
| compatible = "atmel,hlcdc-display-controller"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0>; |
| }; |
| }; |
| |
| hlcdc_pwm: hlcdc-pwm { |
| compatible = "atmel,hlcdc-pwm"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_lcd_pwm>; |
| #pwm-cells = <3>; |
| }; |
| }; |
| |
| dma1: dma-controller@f0004000 { |
| compatible = "atmel,sama5d4-dma"; |
| reg = <0xf0004000 0x200>; |
| interrupts = <50 IRQ_TYPE_LEVEL_HIGH 0>; |
| #dma-cells = <1>; |
| clocks = <&dma1_clk>; |
| clock-names = "dma_clk"; |
| }; |
| |
| isi: isi@f0008000 { |
| compatible = "atmel,at91sam9g45-isi"; |
| reg = <0xf0008000 0x4000>; |
| interrupts = <52 IRQ_TYPE_LEVEL_HIGH 5>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_isi_data_0_7>; |
| clocks = <&isi_clk>; |
| clock-names = "isi_clk"; |
| status = "disabled"; |
| port { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| }; |
| |
| ramc0: ramc@f0010000 { |
| compatible = "atmel,sama5d3-ddramc"; |
| reg = <0xf0010000 0x200>; |
| clocks = <&ddrck>, <&mpddr_clk>; |
| clock-names = "ddrck", "mpddr"; |
| }; |
| |
| dma0: dma-controller@f0014000 { |
| compatible = "atmel,sama5d4-dma"; |
| reg = <0xf0014000 0x200>; |
| interrupts = <8 IRQ_TYPE_LEVEL_HIGH 0>; |
| #dma-cells = <1>; |
| clocks = <&dma0_clk>; |
| clock-names = "dma_clk"; |
| }; |
| |
| pmc: pmc@f0018000 { |
| compatible = "atmel,sama5d3-pmc", "syscon"; |
| reg = <0xf0018000 0x120>; |
| interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
| interrupt-controller; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| #interrupt-cells = <1>; |
| u-boot,dm-pre-reloc; |
| |
| main_rc_osc: main_rc_osc { |
| compatible = "atmel,at91sam9x5-clk-main-rc-osc"; |
| #clock-cells = <0>; |
| interrupt-parent = <&pmc>; |
| interrupts = <AT91_PMC_MOSCRCS>; |
| clock-frequency = <12000000>; |
| clock-accuracy = <100000000>; |
| }; |
| |
| main_osc: main_osc { |
| compatible = "atmel,at91rm9200-clk-main-osc"; |
| #clock-cells = <0>; |
| interrupt-parent = <&pmc>; |
| interrupts = <AT91_PMC_MOSCS>; |
| clocks = <&main_xtal>; |
| }; |
| |
| main: mainck { |
| compatible = "atmel,at91sam9x5-clk-main"; |
| #clock-cells = <0>; |
| interrupt-parent = <&pmc>; |
| interrupts = <AT91_PMC_MOSCSELS>; |
| clocks = <&main_rc_osc &main_osc>; |
| u-boot,dm-pre-reloc; |
| }; |
| |
| plla: pllack@0 { |
| compatible = "atmel,sama5d3-clk-pll"; |
| #clock-cells = <0>; |
| interrupt-parent = <&pmc>; |
| interrupts = <AT91_PMC_LOCKA>; |
| clocks = <&main>; |
| reg = <0>; |
| atmel,clk-input-range = <12000000 12000000>; |
| #atmel,pll-clk-output-range-cells = <4>; |
| atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>; |
| }; |
| |
| plladiv: plladivck { |
| compatible = "atmel,at91sam9x5-clk-plldiv"; |
| #clock-cells = <0>; |
| clocks = <&plla>; |
| }; |
| |
| utmi: utmick { |
| compatible = "atmel,at91sam9x5-clk-utmi"; |
| #clock-cells = <0>; |
| interrupt-parent = <&pmc>; |
| interrupts = <AT91_PMC_LOCKU>; |
| clocks = <&main>; |
| u-boot,dm-pre-reloc; |
| }; |
| |
| mck: masterck { |
| compatible = "atmel,at91sam9x5-clk-master"; |
| #clock-cells = <0>; |
| interrupt-parent = <&pmc>; |
| interrupts = <AT91_PMC_MCKRDY>; |
| clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>; |
| atmel,clk-output-range = <125000000 200000000>; |
| atmel,clk-divisors = <1 2 4 3>; |
| }; |
| |
| h32ck: h32mxck { |
| #clock-cells = <0>; |
| compatible = "atmel,sama5d4-clk-h32mx"; |
| clocks = <&mck>; |
| u-boot,dm-pre-reloc; |
| }; |
| |
| usb: usbck { |
| compatible = "atmel,at91sam9x5-clk-usb"; |
| #clock-cells = <0>; |
| clocks = <&plladiv>, <&utmi>; |
| }; |
| |
| prog: progck { |
| compatible = "atmel,at91sam9x5-clk-programmable"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| interrupt-parent = <&pmc>; |
| clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; |
| |
| prog0: prog@0 { |
| #clock-cells = <0>; |
| reg = <0>; |
| interrupts = <AT91_PMC_PCKRDY(0)>; |
| }; |
| |
| prog1: prog@1 { |
| #clock-cells = <0>; |
| reg = <1>; |
| interrupts = <AT91_PMC_PCKRDY(1)>; |
| }; |
| |
| prog2: prog@2 { |
| #clock-cells = <0>; |
| reg = <2>; |
| interrupts = <AT91_PMC_PCKRDY(2)>; |
| }; |
| }; |
| |
| smd: smdclk { |
| compatible = "atmel,at91sam9x5-clk-smd"; |
| #clock-cells = <0>; |
| clocks = <&plladiv>, <&utmi>; |
| }; |
| |
| systemck { |
| compatible = "atmel,at91rm9200-clk-system"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| u-boot,dm-pre-reloc; |
| |
| ddrck: ddrck@2 { |
| #clock-cells = <0>; |
| reg = <2>; |
| clocks = <&mck>; |
| }; |
| |
| lcdck: lcdck@3 { |
| #clock-cells = <0>; |
| reg = <3>; |
| clocks = <&mck>; |
| }; |
| |
| smdck: smdck@4 { |
| #clock-cells = <0>; |
| reg = <4>; |
| clocks = <&smd>; |
| }; |
| |
| uhpck: uhpcki@6 { |
| #clock-cells = <0>; |
| reg = <6>; |
| clocks = <&usb>; |
| }; |
| |
| udpck: udpck@7 { |
| #clock-cells = <0>; |
| reg = <7>; |
| clocks = <&usb>; |
| }; |
| |
| pck0: pck0@8 { |
| #clock-cells = <0>; |
| reg = <8>; |
| clocks = <&prog0>; |
| }; |
| |
| pck1: pck1@9 { |
| #clock-cells = <0>; |
| reg = <9>; |
| clocks = <&prog1>; |
| }; |
| |
| pck2: pck2@10 { |
| #clock-cells = <0>; |
| reg = <10>; |
| clocks = <&prog2>; |
| }; |
| }; |
| |
| periph32ck { |
| compatible = "atmel,at91sam9x5-clk-peripheral"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&h32ck>; |
| u-boot,dm-pre-reloc; |
| |
| pioD_clk: pioD_clk@5 { |
| u-boot,dm-pre-reloc; |
| #clock-cells = <0>; |
| reg = <5>; |
| }; |
| |
| usart0_clk: usart0_clk@6 { |
| #clock-cells = <0>; |
| reg = <6>; |
| }; |
| |
| usart1_clk: usart1_clk@7 { |
| #clock-cells = <0>; |
| reg = <7>; |
| }; |
| |
| icm_clk: icm_clk@9 { |
| #clock-cells = <0>; |
| reg = <9>; |
| }; |
| |
| aes_clk: aes_clk@12 { |
| #clock-cells = <0>; |
| reg = <12>; |
| }; |
| |
| tdes_clk: tdes_clk@14 { |
| #clock-cells = <0>; |
| reg = <14>; |
| }; |
| |
| sha_clk: sha_clk@15 { |
| #clock-cells = <0>; |
| reg = <15>; |
| }; |
| |
| matrix1_clk: matrix1_clk@17 { |
| #clock-cells = <0>; |
| reg = <17>; |
| }; |
| |
| hsmc_clk: hsmc_clk@22 { |
| #clock-cells = <0>; |
| reg = <22>; |
| }; |
| |
| pioA_clk: pioA_clk@23 { |
| u-boot,dm-pre-reloc; |
| #clock-cells = <0>; |
| reg = <23>; |
| }; |
| |
| pioB_clk: pioB_clk@24 { |
| u-boot,dm-pre-reloc; |
| #clock-cells = <0>; |
| reg = <24>; |
| }; |
| |
| pioC_clk: pioC_clk@25 { |
| u-boot,dm-pre-reloc; |
| #clock-cells = <0>; |
| reg = <25>; |
| }; |
| |
| pioE_clk: pioE_clk@26 { |
| u-boot,dm-pre-reloc; |
| #clock-cells = <0>; |
| reg = <26>; |
| }; |
| |
| uart0_clk: uart0_clk@27 { |
| #clock-cells = <0>; |
| reg = <27>; |
| }; |
| |
| uart1_clk: uart1_clk@28 { |
| #clock-cells = <0>; |
| reg = <28>; |
| }; |
| |
| usart2_clk: usart2_clk@29 { |
| #clock-cells = <0>; |
| reg = <29>; |
| }; |
| |
| usart3_clk: usart3_clk@30 { |
| u-boot,dm-pre-reloc; |
| #clock-cells = <0>; |
| reg = <30>; |
| }; |
| |
| usart4_clk: usart4_clk@31 { |
| #clock-cells = <0>; |
| reg = <31>; |
| }; |
| |
| twi0_clk: twi0_clk@32 { |
| reg = <32>; |
| #clock-cells = <0>; |
| }; |
| |
| twi1_clk: twi1_clk@33 { |
| #clock-cells = <0>; |
| reg = <33>; |
| }; |
| |
| twi2_clk: twi2_clk@34 { |
| #clock-cells = <0>; |
| reg = <34>; |
| }; |
| |
| mci0_clk: mci0_clk@35 { |
| #clock-cells = <0>; |
| reg = <35>; |
| }; |
| |
| mci1_clk: mci1_clk@36 { |
| u-boot,dm-pre-reloc; |
| #clock-cells = <0>; |
| reg = <36>; |
| }; |
| |
| spi0_clk: spi0_clk@37 { |
| u-boot,dm-pre-reloc; |
| #clock-cells = <0>; |
| reg = <37>; |
| }; |
| |
| spi1_clk: spi1_clk@38 { |
| #clock-cells = <0>; |
| reg = <38>; |
| }; |
| |
| spi2_clk: spi2_clk@39 { |
| #clock-cells = <0>; |
| reg = <39>; |
| }; |
| |
| tcb0_clk: tcb0_clk@40 { |
| #clock-cells = <0>; |
| reg = <40>; |
| }; |
| |
| tcb1_clk: tcb1_clk@41 { |
| #clock-cells = <0>; |
| reg = <41>; |
| }; |
| |
| tcb2_clk: tcb2_clk@42 { |
| #clock-cells = <0>; |
| reg = <42>; |
| }; |
| |
| pwm_clk: pwm_clk@43 { |
| #clock-cells = <0>; |
| reg = <43>; |
| }; |
| |
| adc_clk: adc_clk@44 { |
| #clock-cells = <0>; |
| reg = <44>; |
| }; |
| |
| dbgu_clk: dbgu_clk@45 { |
| #clock-cells = <0>; |
| reg = <45>; |
| }; |
| |
| uhphs_clk: uhphs_clk@46 { |
| #clock-cells = <0>; |
| reg = <46>; |
| }; |
| |
| udphs_clk: udphs_clk@47 { |
| #clock-cells = <0>; |
| reg = <47>; |
| }; |
| |
| ssc0_clk: ssc0_clki@48 { |
| #clock-cells = <0>; |
| reg = <48>; |
| }; |
| |
| ssc1_clk: ssc1_clk@49 { |
| #clock-cells = <0>; |
| reg = <49>; |
| }; |
| |
| trng_clk: trng_clk@53 { |
| #clock-cells = <0>; |
| reg = <53>; |
| }; |
| |
| macb0_clk: macb0_clk@54 { |
| #clock-cells = <0>; |
| reg = <54>; |
| }; |
| |
| macb1_clk: macb1_clk@55 { |
| #clock-cells = <0>; |
| reg = <55>; |
| }; |
| |
| fuse_clk: fuse_clk@57 { |
| #clock-cells = <0>; |
| reg = <57>; |
| }; |
| |
| securam_clk: securam_clk@59 { |
| #clock-cells = <0>; |
| reg = <59>; |
| }; |
| |
| smd_clk: smd_clk@61 { |
| #clock-cells = <0>; |
| reg = <61>; |
| }; |
| |
| twi3_clk: twi3_clk@62 { |
| #clock-cells = <0>; |
| reg = <62>; |
| }; |
| |
| catb_clk: catb_clk@63 { |
| #clock-cells = <0>; |
| reg = <63>; |
| }; |
| }; |
| |
| periph64ck { |
| compatible = "atmel,at91sam9x5-clk-peripheral"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&mck>; |
| |
| dma0_clk: dma0_clk@8 { |
| #clock-cells = <0>; |
| reg = <8>; |
| }; |
| |
| cpkcc_clk: cpkcc_clk@10 { |
| #clock-cells = <0>; |
| reg = <10>; |
| }; |
| |
| aesb_clk: aesb_clk@13 { |
| #clock-cells = <0>; |
| reg = <13>; |
| }; |
| |
| mpddr_clk: mpddr_clk@16 { |
| #clock-cells = <0>; |
| reg = <16>; |
| }; |
| |
| matrix0_clk: matrix0_clk@18 { |
| #clock-cells = <0>; |
| reg = <18>; |
| }; |
| |
| vdec_clk: vdec_clk@19 { |
| #clock-cells = <0>; |
| reg = <19>; |
| }; |
| |
| dma1_clk: dma1_clk@50 { |
| #clock-cells = <0>; |
| reg = <50>; |
| }; |
| |
| lcdc_clk: lcdc_clk@51 { |
| #clock-cells = <0>; |
| reg = <51>; |
| }; |
| |
| isi_clk: isi_clk@52 { |
| #clock-cells = <0>; |
| reg = <52>; |
| }; |
| }; |
| }; |
| |
| mmc0: mmc@f8000000 { |
| compatible = "atmel,hsmci"; |
| reg = <0xf8000000 0x600>; |
| interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>; |
| dmas = <&dma1 |
| (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
| | AT91_XDMAC_DT_PERID(0))>; |
| dma-names = "rxtx"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3>; |
| status = "disabled"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&mci0_clk>; |
| clock-names = "mci_clk"; |
| }; |
| |
| uart0: serial@f8004000 { |
| compatible = "atmel,at91sam9260-usart"; |
| reg = <0xf8004000 0x100>; |
| interrupts = <27 IRQ_TYPE_LEVEL_HIGH 5>; |
| dmas = <&dma1 |
| (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
| | AT91_XDMAC_DT_PERID(22))>, |
| <&dma1 |
| (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
| | AT91_XDMAC_DT_PERID(23))>; |
| dma-names = "tx", "rx"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart0>; |
| clocks = <&uart0_clk>; |
| clock-names = "usart"; |
| status = "disabled"; |
| }; |
| |
| ssc0: ssc@f8008000 { |
| compatible = "atmel,at91sam9g45-ssc"; |
| reg = <0xf8008000 0x4000>; |
| interrupts = <48 IRQ_TYPE_LEVEL_HIGH 0>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; |
| dmas = <&dma1 |
| (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
| | AT91_XDMAC_DT_PERID(26))>, |
| <&dma1 |
| (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
| | AT91_XDMAC_DT_PERID(27))>; |
| dma-names = "tx", "rx"; |
| clocks = <&ssc0_clk>; |
| clock-names = "pclk"; |
| status = "disabled"; |
| }; |
| |
| pwm0: pwm@f800c000 { |
| compatible = "atmel,sama5d3-pwm"; |
| reg = <0xf800c000 0x300>; |
| interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>; |
| #pwm-cells = <3>; |
| clocks = <&pwm_clk>; |
| status = "disabled"; |
| }; |
| |
| spi0: spi@f8010000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "atmel,at91rm9200-spi"; |
| reg = <0xf8010000 0x100>; |
| interrupts = <37 IRQ_TYPE_LEVEL_HIGH 3>; |
| dmas = <&dma1 |
| (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
| | AT91_XDMAC_DT_PERID(10))>, |
| <&dma1 |
| (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
| | AT91_XDMAC_DT_PERID(11))>; |
| dma-names = "tx", "rx"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_spi0>; |
| clocks = <&spi0_clk>; |
| clock-names = "spi_clk"; |
| status = "disabled"; |
| }; |
| |
| i2c0: i2c@f8014000 { |
| compatible = "atmel,sama5d4-i2c"; |
| reg = <0xf8014000 0x4000>; |
| interrupts = <32 IRQ_TYPE_LEVEL_HIGH 6>; |
| dmas = <&dma1 |
| (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
| | AT91_XDMAC_DT_PERID(2))>, |
| <&dma1 |
| (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
| | AT91_XDMAC_DT_PERID(3))>; |
| dma-names = "tx", "rx"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_i2c0>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&twi0_clk>; |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@f8018000 { |
| compatible = "atmel,sama5d4-i2c"; |
| reg = <0xf8018000 0x4000>; |
| interrupts = <33 IRQ_TYPE_LEVEL_HIGH 6>; |
| dmas = <&dma1 |
| (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
| | AT91_XDMAC_DT_PERID(4))>, |
| <&dma1 |
| (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
| | AT91_XDMAC_DT_PERID(5))>; |
| dma-names = "tx", "rx"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_i2c1>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&twi1_clk>; |
| status = "disabled"; |
| }; |
| |
| tcb0: timer@f801c000 { |
| compatible = "atmel,at91sam9x5-tcb"; |
| reg = <0xf801c000 0x100>; |
| interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&tcb0_clk>, <&clk32k>; |
| clock-names = "t0_clk", "slow_clk"; |
| }; |
| |
| macb0: ethernet@f8020000 { |
| compatible = "atmel,sama5d4-gem"; |
| reg = <0xf8020000 0x100>; |
| interrupts = <54 IRQ_TYPE_LEVEL_HIGH 3>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_macb0_rmii>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&macb0_clk>, <&macb0_clk>; |
| clock-names = "hclk", "pclk"; |
| status = "disabled"; |
| }; |
| |
| i2c2: i2c@f8024000 { |
| compatible = "atmel,sama5d4-i2c"; |
| reg = <0xf8024000 0x4000>; |
| interrupts = <34 IRQ_TYPE_LEVEL_HIGH 6>; |
| dmas = <&dma1 |
| (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
| | AT91_XDMAC_DT_PERID(6))>, |
| <&dma1 |
| (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
| | AT91_XDMAC_DT_PERID(7))>; |
| dma-names = "tx", "rx"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_i2c2>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&twi2_clk>; |
| status = "disabled"; |
| }; |
| |
| sfr: sfr@f8028000 { |
| compatible = "atmel,sama5d4-sfr", "syscon"; |
| reg = <0xf8028000 0x60>; |
| }; |
| |
| usart0: serial@f802c000 { |
| compatible = "atmel,at91sam9260-usart"; |
| reg = <0xf802c000 0x100>; |
| interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; |
| dmas = <&dma0 |
| (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
| | AT91_XDMAC_DT_PERID(36))>, |
| <&dma0 |
| (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
| | AT91_XDMAC_DT_PERID(37))>; |
| dma-names = "tx", "rx"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts &pinctrl_usart0_cts>; |
| clocks = <&usart0_clk>; |
| clock-names = "usart"; |
| status = "disabled"; |
| }; |
| |
| usart1: serial@f8030000 { |
| compatible = "atmel,at91sam9260-usart"; |
| reg = <0xf8030000 0x100>; |
| interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; |
| dmas = <&dma0 |
| (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
| | AT91_XDMAC_DT_PERID(38))>, |
| <&dma0 |
| (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
| | AT91_XDMAC_DT_PERID(39))>; |
| dma-names = "tx", "rx"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts &pinctrl_usart1_cts>; |
| clocks = <&usart1_clk>; |
| clock-names = "usart"; |
| status = "disabled"; |
| }; |
| |
| mmc1: mmc@fc000000 { |
| compatible = "atmel,hsmci"; |
| reg = <0xfc000000 0x600>; |
| interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; |
| dmas = <&dma1 |
| (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
| | AT91_XDMAC_DT_PERID(1))>; |
| dma-names = "rxtx"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>; |
| status = "disabled"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&mci1_clk>; |
| clock-names = "mci_clk"; |
| }; |
| |
| uart1: serial@fc004000 { |
| compatible = "atmel,at91sam9260-usart"; |
| reg = <0xfc004000 0x100>; |
| interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; |
| dmas = <&dma1 |
| (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
| | AT91_XDMAC_DT_PERID(24))>, |
| <&dma1 |
| (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
| | AT91_XDMAC_DT_PERID(25))>; |
| dma-names = "tx", "rx"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart1>; |
| clocks = <&uart1_clk>; |
| clock-names = "usart"; |
| status = "disabled"; |
| }; |
| |
| usart2: serial@fc008000 { |
| compatible = "atmel,at91sam9260-usart"; |
| reg = <0xfc008000 0x100>; |
| interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>; |
| dmas = <&dma1 |
| (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
| | AT91_XDMAC_DT_PERID(16))>, |
| <&dma1 |
| (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
| | AT91_XDMAC_DT_PERID(17))>; |
| dma-names = "tx", "rx"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rts &pinctrl_usart2_cts>; |
| clocks = <&usart2_clk>; |
| clock-names = "usart"; |
| status = "disabled"; |
| }; |
| |
| usart3: serial@fc00c000 { |
| compatible = "atmel,at91sam9260-usart"; |
| reg = <0xfc00c000 0x100>; |
| interrupts = <30 IRQ_TYPE_LEVEL_HIGH 5>; |
| dmas = <&dma1 |
| (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
| | AT91_XDMAC_DT_PERID(18))>, |
| <&dma1 |
| (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
| | AT91_XDMAC_DT_PERID(19))>; |
| dma-names = "tx", "rx"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_usart3>; |
| clocks = <&usart3_clk>; |
| clock-names = "usart"; |
| status = "disabled"; |
| }; |
| |
| usart4: serial@fc010000 { |
| compatible = "atmel,at91sam9260-usart"; |
| reg = <0xfc010000 0x100>; |
| interrupts = <31 IRQ_TYPE_LEVEL_HIGH 5>; |
| dmas = <&dma1 |
| (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
| | AT91_XDMAC_DT_PERID(20))>, |
| <&dma1 |
| (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
| | AT91_XDMAC_DT_PERID(21))>; |
| dma-names = "tx", "rx"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_usart4>; |
| clocks = <&usart4_clk>; |
| clock-names = "usart"; |
| status = "disabled"; |
| }; |
| |
| ssc1: ssc@fc014000 { |
| compatible = "atmel,at91sam9g45-ssc"; |
| reg = <0xfc014000 0x4000>; |
| interrupts = <49 IRQ_TYPE_LEVEL_HIGH 0>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; |
| dmas = <&dma1 |
| (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
| | AT91_XDMAC_DT_PERID(28))>, |
| <&dma1 |
| (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
| | AT91_XDMAC_DT_PERID(29))>; |
| dma-names = "tx", "rx"; |
| clocks = <&ssc1_clk>; |
| clock-names = "pclk"; |
| status = "disabled"; |
| }; |
| |
| spi1: spi@fc018000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "atmel,at91rm9200-spi"; |
| reg = <0xfc018000 0x100>; |
| interrupts = <38 IRQ_TYPE_LEVEL_HIGH 3>; |
| dmas = <&dma1 |
| (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
| | AT91_XDMAC_DT_PERID(12))>, |
| <&dma1 |
| (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
| | AT91_XDMAC_DT_PERID(13))>; |
| dma-names = "tx", "rx"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_spi1>; |
| clocks = <&spi1_clk>; |
| clock-names = "spi_clk"; |
| status = "disabled"; |
| }; |
| |
| spi2: spi@fc01c000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "atmel,at91rm9200-spi"; |
| reg = <0xfc01c000 0x100>; |
| interrupts = <39 IRQ_TYPE_LEVEL_HIGH 3>; |
| dmas = <&dma1 |
| (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
| | AT91_XDMAC_DT_PERID(14))>, |
| <&dma1 |
| (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
| | AT91_XDMAC_DT_PERID(15))>; |
| dma-names = "tx", "rx"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_spi2>; |
| clocks = <&spi2_clk>; |
| clock-names = "spi_clk"; |
| status = "disabled"; |
| }; |
| |
| tcb1: timer@fc020000 { |
| compatible = "atmel,at91sam9x5-tcb"; |
| reg = <0xfc020000 0x100>; |
| interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&tcb1_clk>, <&clk32k>; |
| clock-names = "t0_clk", "slow_clk"; |
| }; |
| |
| macb1: ethernet@fc028000 { |
| compatible = "atmel,sama5d4-gem"; |
| reg = <0xfc028000 0x100>; |
| interrupts = <55 IRQ_TYPE_LEVEL_HIGH 3>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_macb1_rmii>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&macb1_clk>, <&macb1_clk>; |
| clock-names = "hclk", "pclk"; |
| status = "disabled"; |
| }; |
| |
| trng@fc030000 { |
| compatible = "atmel,at91sam9g45-trng"; |
| reg = <0xfc030000 0x100>; |
| interrupts = <53 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&trng_clk>; |
| }; |
| |
| adc0: adc@fc034000 { |
| compatible = "atmel,at91sam9x5-adc"; |
| reg = <0xfc034000 0x100>; |
| interrupts = <44 IRQ_TYPE_LEVEL_HIGH 5>; |
| clocks = <&adc_clk>, |
| <&adc_op_clk>; |
| clock-names = "adc_clk", "adc_op_clk"; |
| atmel,adc-channels-used = <0x01f>; |
| atmel,adc-startup-time = <40>; |
| atmel,adc-use-external-triggers; |
| atmel,adc-vref = <3000>; |
| atmel,adc-res = <8 10>; |
| atmel,adc-sample-hold-time = <11>; |
| atmel,adc-res-names = "lowres", "highres"; |
| atmel,adc-ts-pressure-threshold = <10000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| |
| trigger@0 { |
| trigger-name = "external-rising"; |
| trigger-value = <0x1>; |
| trigger-external; |
| reg = <0>; |
| }; |
| trigger@1 { |
| trigger-name = "external-falling"; |
| trigger-value = <0x2>; |
| trigger-external; |
| reg = <1>; |
| }; |
| trigger@2 { |
| trigger-name = "external-any"; |
| trigger-value = <0x3>; |
| trigger-external; |
| reg = <2>; |
| }; |
| trigger@3 { |
| trigger-name = "continuous"; |
| trigger-value = <0x6>; |
| reg = <3>; |
| }; |
| }; |
| |
| aes@fc044000 { |
| compatible = "atmel,at91sam9g46-aes"; |
| reg = <0xfc044000 0x100>; |
| interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; |
| dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
| | AT91_XDMAC_DT_PERID(41))>, |
| <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
| | AT91_XDMAC_DT_PERID(40))>; |
| dma-names = "tx", "rx"; |
| clocks = <&aes_clk>; |
| clock-names = "aes_clk"; |
| status = "okay"; |
| }; |
| |
| tdes@fc04c000 { |
| compatible = "atmel,at91sam9g46-tdes"; |
| reg = <0xfc04c000 0x100>; |
| interrupts = <14 IRQ_TYPE_LEVEL_HIGH 0>; |
| dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
| | AT91_XDMAC_DT_PERID(42))>, |
| <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
| | AT91_XDMAC_DT_PERID(43))>; |
| dma-names = "tx", "rx"; |
| clocks = <&tdes_clk>; |
| clock-names = "tdes_clk"; |
| status = "okay"; |
| }; |
| |
| sha@fc050000 { |
| compatible = "atmel,at91sam9g46-sha"; |
| reg = <0xfc050000 0x100>; |
| interrupts = <15 IRQ_TYPE_LEVEL_HIGH 0>; |
| dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
| | AT91_XDMAC_DT_PERID(44))>; |
| dma-names = "tx"; |
| clocks = <&sha_clk>; |
| clock-names = "sha_clk"; |
| status = "okay"; |
| }; |
| |
| rstc@fc068600 { |
| compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc"; |
| reg = <0xfc068600 0x10>; |
| clocks = <&clk32k>; |
| }; |
| |
| shdwc@fc068610 { |
| compatible = "atmel,at91sam9x5-shdwc"; |
| reg = <0xfc068610 0x10>; |
| clocks = <&clk32k>; |
| }; |
| |
| pit: timer@fc068630 { |
| compatible = "atmel,at91sam9260-pit"; |
| reg = <0xfc068630 0x10>; |
| interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; |
| clocks = <&h32ck>; |
| }; |
| |
| watchdog@fc068640 { |
| compatible = "atmel,sama5d4-wdt"; |
| reg = <0xfc068640 0x10>; |
| interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>; |
| clocks = <&clk32k>; |
| status = "disabled"; |
| }; |
| |
| sckc@fc068650 { |
| compatible = "atmel,at91sam9x5-sckc"; |
| reg = <0xfc068650 0x4>; |
| |
| slow_rc_osc: slow_rc_osc { |
| compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; |
| #clock-cells = <0>; |
| clock-frequency = <32768>; |
| clock-accuracy = <250000000>; |
| atmel,startup-time-usec = <75>; |
| }; |
| |
| slow_osc: slow_osc { |
| compatible = "atmel,at91sam9x5-clk-slow-osc"; |
| #clock-cells = <0>; |
| clocks = <&slow_xtal>; |
| atmel,startup-time-usec = <1200000>; |
| }; |
| |
| clk32k: slowck { |
| compatible = "atmel,at91sam9x5-clk-slow"; |
| #clock-cells = <0>; |
| clocks = <&slow_rc_osc &slow_osc>; |
| }; |
| }; |
| |
| rtc@fc0686b0 { |
| compatible = "atmel,at91rm9200-rtc"; |
| reg = <0xfc0686b0 0x30>; |
| interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
| clocks = <&clk32k>; |
| }; |
| |
| dbgu: serial@fc069000 { |
| compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; |
| reg = <0xfc069000 0x200>; |
| interrupts = <45 IRQ_TYPE_LEVEL_HIGH 7>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_dbgu>; |
| clocks = <&dbgu_clk>; |
| clock-names = "usart"; |
| status = "disabled"; |
| }; |
| |
| pioA: gpio@fc06a000 { |
| compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| reg = <0xfc06a000 0x100>; |
| interrupts = <23 IRQ_TYPE_LEVEL_HIGH 1>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&pioA_clk>; |
| }; |
| |
| pioB: gpio@fc06b000 { |
| compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| reg = <0xfc06b000 0x100>; |
| interrupts = <24 IRQ_TYPE_LEVEL_HIGH 1>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&pioB_clk>; |
| }; |
| |
| pioC: gpio@fc06c000 { |
| compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| reg = <0xfc06c000 0x100>; |
| interrupts = <25 IRQ_TYPE_LEVEL_HIGH 1>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&pioC_clk>; |
| u-boot,dm-pre-reloc; |
| }; |
| |
| pioD: gpio@fc068000 { |
| compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| reg = <0xfc068000 0x100>; |
| interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&pioD_clk>; |
| }; |
| |
| pioE: gpio@fc06d000 { |
| compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| reg = <0xfc06d000 0x100>; |
| interrupts = <26 IRQ_TYPE_LEVEL_HIGH 1>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&pioE_clk>; |
| }; |
| |
| pinctrl@fc06a000 { |
| u-boot,dm-pre-reloc; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; |
| ranges = <0xfc068000 0xfc068000 0x100 |
| 0xfc06a000 0xfc06a000 0x4000>; |
| /* WARNING: revisit as pin spec has changed */ |
| atmel,mux-mask = < |
| /* A B C */ |
| 0xffffffff 0x3ffcfe7c 0x1c010101 /* pioA */ |
| 0x7fffffff 0xfffccc3a 0x3f00cc3a /* pioB */ |
| 0xffffffff 0x3ff83fff 0xff00ffff /* pioC */ |
| 0x0003ff00 0x8002a800 0x00000000 /* pioD */ |
| 0xffffffff 0x7fffffff 0x76fff1bf /* pioE */ |
| >; |
| reg = < 0xfc06a000 0x100 |
| 0xfc06b000 0x100 |
| 0xfc06c000 0x100 |
| 0xfc068000 0x100 |
| 0xfc06d000 0x100 |
| >; |
| |
| /* pinctrl pin settings */ |
| adc0 { |
| pinctrl_adc0_adtrg: adc0_adtrg { |
| atmel,pins = |
| <AT91_PIOE 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* conflicts with USBA_VBUS */ |
| }; |
| pinctrl_adc0_ad0: adc0_ad0 { |
| atmel,pins = |
| <AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; |
| }; |
| pinctrl_adc0_ad1: adc0_ad1 { |
| atmel,pins = |
| <AT91_PIOC 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; |
| }; |
| pinctrl_adc0_ad2: adc0_ad2 { |
| atmel,pins = |
| <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; |
| }; |
| pinctrl_adc0_ad3: adc0_ad3 { |
| atmel,pins = |
| <AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; |
| }; |
| pinctrl_adc0_ad4: adc0_ad4 { |
| atmel,pins = |
| <AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; |
| }; |
| }; |
| |
| dbgu { |
| pinctrl_dbgu: dbgu-0 { |
| atmel,pins = |
| <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE>, /* conflicts with D14 and TDI */ |
| <AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* conflicts with D15 and TDO */ |
| }; |
| }; |
| |
| i2c0 { |
| pinctrl_i2c0: i2c0-0 { |
| atmel,pins = |
| <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE |
| AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; |
| }; |
| }; |
| |
| i2c1 { |
| pinctrl_i2c1: i2c1-0 { |
| atmel,pins = |
| <AT91_PIOE 29 AT91_PERIPH_C AT91_PINCTRL_NONE /* TWD1, conflicts with UART0 RX and DIBP */ |
| AT91_PIOE 30 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* TWCK1, conflicts with UART0 TX and DIBN */ |
| }; |
| }; |
| |
| i2c2 { |
| pinctrl_i2c2: i2c2-0 { |
| atmel,pins = |
| <AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* TWD2, conflicts with RD0 and PWML1 */ |
| AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* TWCK2, conflicts with RF0 */ |
| }; |
| }; |
| |
| isi { |
| pinctrl_isi_data_0_7: isi-0-data-0-7 { |
| atmel,pins = |
| <AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D0 */ |
| AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D1 */ |
| AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D2 */ |
| AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D3 */ |
| AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D4 */ |
| AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D5 */ |
| AT91_PIOC 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D6 */ |
| AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D7 */ |
| AT91_PIOB 1 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_PCK, conflict with G0_RXCK */ |
| AT91_PIOB 3 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_VSYNC */ |
| AT91_PIOB 4 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_HSYNC */ |
| }; |
| pinctrl_isi_data_8_9: isi-0-data-8-9 { |
| atmel,pins = |
| <AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_D8, conflicts with SPI0_MISO, PWMH2 */ |
| AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_D9, conflicts with SPI0_MOSI, PWML2 */ |
| }; |
| pinctrl_isi_data_10_11: isi-0-data-10-11 { |
| atmel,pins = |
| <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_D10, conflicts with SPI0_SPCK, PWMH3 */ |
| AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_D11, conflicts with SPI0_NPCS0, PWML3 */ |
| }; |
| }; |
| |
| lcd { |
| pinctrl_lcd_base: lcd-base-0 { |
| atmel,pins = |
| <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDVSYNC */ |
| AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDHSYNC */ |
| AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDDEN */ |
| AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPCK */ |
| }; |
| pinctrl_lcd_pwm: lcd-pwm-0 { |
| atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPWM */ |
| }; |
| pinctrl_lcd_rgb444: lcd-rgb-0 { |
| atmel,pins = |
| <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */ |
| AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */ |
| AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */ |
| AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */ |
| AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */ |
| AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */ |
| AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */ |
| AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */ |
| AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */ |
| AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */ |
| AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */ |
| AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD11 pin */ |
| }; |
| pinctrl_lcd_rgb565: lcd-rgb-1 { |
| atmel,pins = |
| <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */ |
| AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */ |
| AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */ |
| AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */ |
| AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */ |
| AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */ |
| AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */ |
| AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */ |
| AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */ |
| AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */ |
| AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */ |
| AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */ |
| AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */ |
| AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */ |
| AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */ |
| AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD15 pin */ |
| }; |
| pinctrl_lcd_rgb666: lcd-rgb-2 { |
| atmel,pins = |
| <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */ |
| AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */ |
| AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */ |
| AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */ |
| AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */ |
| AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */ |
| AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */ |
| AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */ |
| AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */ |
| AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */ |
| AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */ |
| AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */ |
| AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */ |
| AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */ |
| AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */ |
| AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */ |
| AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */ |
| AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */ |
| }; |
| pinctrl_lcd_rgb777: lcd-rgb-3 { |
| atmel,pins = |
| /* LCDDAT0 conflicts with TMS */ |
| <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */ |
| AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */ |
| AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */ |
| AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */ |
| AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */ |
| AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */ |
| AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */ |
| /* LCDDAT8 conflicts with TCK */ |
| AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */ |
| AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */ |
| AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */ |
| AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */ |
| AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */ |
| AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */ |
| AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */ |
| /* LCDDAT16 conflicts with NTRST */ |
| AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD17 pin */ |
| AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */ |
| AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */ |
| AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */ |
| AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */ |
| AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */ |
| AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */ |
| }; |
| pinctrl_lcd_rgb888: lcd-rgb-4 { |
| atmel,pins = |
| <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */ |
| AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */ |
| AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */ |
| AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */ |
| AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */ |
| AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */ |
| AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */ |
| AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */ |
| AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */ |
| AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */ |
| AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */ |
| AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */ |
| AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */ |
| AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */ |
| AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */ |
| AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */ |
| AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD16 pin */ |
| AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD17 pin */ |
| AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */ |
| AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */ |
| AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */ |
| AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */ |
| AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */ |
| AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */ |
| }; |
| }; |
| |
| macb0 { |
| pinctrl_macb0_rmii: macb0_rmii-0 { |
| atmel,pins = |
| <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX0 */ |
| AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX1 */ |
| AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX0 */ |
| AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX1 */ |
| AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXDV */ |
| AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXER */ |
| AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXEN */ |
| AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXCK */ |
| AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDC */ |
| AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDIO */ |
| >; |
| }; |
| }; |
| |
| macb1 { |
| pinctrl_macb1_rmii: macb1_rmii-0 { |
| atmel,pins = |
| <AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_TX0 */ |
| AT91_PIOA 15 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_TX1 */ |
| AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_RX0 */ |
| AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_RX1 */ |
| AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_RXDV */ |
| AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_RXER */ |
| AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_TXEN */ |
| AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_TXCK */ |
| AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_MDC */ |
| AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_MDIO */ |
| >; |
| }; |
| }; |
| |
| mmc0 { |
| pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 { |
| atmel,pins = |
| <AT91_PIOC 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* MCI0_CK, conflict with PCK1(ISI_MCK) */ |
| AT91_PIOC 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_CDA, conflict with NAND_D0 */ |
| AT91_PIOC 6 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA0, conflict with NAND_D1 */ |
| >; |
| }; |
| pinctrl_mmc0_dat1_3: mmc0_dat1_3 { |
| atmel,pins = |
| <AT91_PIOC 7 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA1, conflict with NAND_D2 */ |
| AT91_PIOC 8 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA2, conflict with NAND_D3 */ |
| AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA3, conflict with NAND_D4 */ |
| >; |
| }; |
| pinctrl_mmc0_dat4_7: mmc0_dat4_7 { |
| atmel,pins = |
| <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA4, conflict with NAND_D5 */ |
| AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA5, conflict with NAND_D6 */ |
| AT91_PIOC 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA6, conflict with NAND_D7 */ |
| AT91_PIOC 13 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA7, conflict with NAND_OE */ |
| >; |
| }; |
| }; |
| |
| mmc1 { |
| u-boot,dm-pre-reloc; |
| pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 { |
| u-boot,dm-pre-reloc; |
| atmel,pins = |
| <AT91_PIOE 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* MCI1_CK */ |
| AT91_PIOE 19 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_CDA */ |
| AT91_PIOE 20 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA0 */ |
| >; |
| }; |
| pinctrl_mmc1_dat1_3: mmc1_dat1_3 { |
| u-boot,dm-pre-reloc; |
| atmel,pins = |
| <AT91_PIOE 21 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA1 */ |
| AT91_PIOE 22 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA2 */ |
| AT91_PIOE 23 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA3 */ |
| >; |
| }; |
| }; |
| |
| nand0 { |
| pinctrl_nand: nand-0 { |
| atmel,pins = |
| <AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC13 periph A Read Enable */ |
| AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC14 periph A Write Enable */ |
| |
| AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC17 ALE */ |
| AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC18 CLE */ |
| |
| AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC15 NCS3/Chip Enable */ |
| AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC16 NANDRDY */ |
| AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC5 Data bit 0 */ |
| AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 Data bit 1 */ |
| AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 Data bit 2 */ |
| AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 Data bit 3 */ |
| AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC9 Data bit 4 */ |
| AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC10 Data bit 5 */ |
| AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC11 periph A Data bit 6 */ |
| AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC12 periph A Data bit 7 */ |
| }; |
| }; |
| |
| spi0 { |
| u-boot,dm-pre-reloc; |
| pinctrl_spi0: spi0-0 { |
| u-boot,dm-pre-reloc; |
| atmel,pins = |
| <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MISO */ |
| AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MOSI */ |
| AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_SPCK */ |
| >; |
| }; |
| }; |
| |
| ssc0 { |
| pinctrl_ssc0_tx: ssc0_tx { |
| atmel,pins = |
| <AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* TK0 */ |
| AT91_PIOB 31 AT91_PERIPH_B AT91_PINCTRL_NONE /* TF0 */ |
| AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TD0 */ |
| }; |
| |
| pinctrl_ssc0_rx: ssc0_rx { |
| atmel,pins = |
| <AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* RK0 */ |
| AT91_PIOB 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* RF0 */ |
| AT91_PIOB 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* RD0 */ |
| }; |
| }; |
| |
| ssc1 { |
| pinctrl_ssc1_tx: ssc1_tx { |
| atmel,pins = |
| <AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* TK1 */ |
| AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* TF1 */ |
| AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TD1 */ |
| }; |
| |
| pinctrl_ssc1_rx: ssc1_rx { |
| atmel,pins = |
| <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* RK1 */ |
| AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* RF1 */ |
| AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* RD1 */ |
| }; |
| }; |
| |
| spi1 { |
| pinctrl_spi1: spi1-0 { |
| atmel,pins = |
| <AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI1_MISO */ |
| AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI1_MOSI */ |
| AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI1_SPCK */ |
| >; |
| }; |
| }; |
| |
| spi2 { |
| pinctrl_spi2: spi2-0 { |
| atmel,pins = |
| <AT91_PIOD 11 AT91_PERIPH_B AT91_PINCTRL_NONE /* SPI2_MISO conflicts with RTS0 */ |
| AT91_PIOD 13 AT91_PERIPH_B AT91_PINCTRL_NONE /* SPI2_MOSI conflicts with TXD0 */ |
| AT91_PIOD 15 AT91_PERIPH_B AT91_PINCTRL_NONE /* SPI2_SPCK conflicts with RTS1 */ |
| >; |
| }; |
| }; |
| |
| uart0 { |
| pinctrl_uart0: uart0-0 { |
| atmel,pins = |
| <AT91_PIOE 29 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD */ |
| AT91_PIOE 30 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD */ |
| >; |
| }; |
| }; |
| |
| uart1 { |
| pinctrl_uart1: uart1-0 { |
| atmel,pins = |
| <AT91_PIOC 25 AT91_PERIPH_C AT91_PINCTRL_NONE /* RXD */ |
| AT91_PIOC 26 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* TXD */ |
| >; |
| }; |
| }; |
| |
| usart0 { |
| pinctrl_usart0: usart0-0 { |
| atmel,pins = |
| <AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* RXD */ |
| AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* TXD */ |
| >; |
| }; |
| pinctrl_usart0_rts: usart0_rts-0 { |
| atmel,pins = <AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; |
| }; |
| pinctrl_usart0_cts: usart0_cts-0 { |
| atmel,pins = <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; |
| }; |
| }; |
| |
| usart1 { |
| pinctrl_usart1: usart1-0 { |
| atmel,pins = |
| <AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* RXD */ |
| AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* TXD */ |
| >; |
| }; |
| pinctrl_usart1_rts: usart1_rts-0 { |
| atmel,pins = <AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; |
| }; |
| pinctrl_usart1_cts: usart1_cts-0 { |
| atmel,pins = <AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; |
| }; |
| }; |
| |
| usart2 { |
| pinctrl_usart2: usart2-0 { |
| atmel,pins = |
| <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD - conflicts with G0_CRS, ISI_HSYNC */ |
| AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD - conflicts with G0_COL, PCK2 */ |
| >; |
| }; |
| pinctrl_usart2_rts: usart2_rts-0 { |
| atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_RX3, PWMH1 */ |
| }; |
| pinctrl_usart2_cts: usart2_cts-0 { |
| atmel,pins = <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_TXER, ISI_VSYNC */ |
| }; |
| }; |
| |
| usart3 { |
| u-boot,dm-pre-reloc; |
| pinctrl_usart3: usart3-0 { |
| u-boot,dm-pre-reloc; |
| atmel,pins = |
| <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD */ |
| AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD */ |
| >; |
| }; |
| }; |
| |
| usart4 { |
| pinctrl_usart4: usart4-0 { |
| atmel,pins = |
| <AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD */ |
| AT91_PIOE 27 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD */ |
| >; |
| }; |
| pinctrl_usart4_rts: usart4_rts-0 { |
| atmel,pins = <AT91_PIOE 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with NWAIT, A19 */ |
| }; |
| pinctrl_usart4_cts: usart4_cts-0 { |
| atmel,pins = <AT91_PIOE 0 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with A0/NBS0, MCI0_CDB */ |
| }; |
| }; |
| }; |
| |
| aic: interrupt-controller@fc06e000 { |
| #interrupt-cells = <3>; |
| compatible = "atmel,sama5d4-aic"; |
| interrupt-controller; |
| reg = <0xfc06e000 0x200>; |
| atmel,external-irqs = <56>; |
| }; |
| }; |
| }; |
| }; |