armv8: lx2160ardb : Add support for LX2160ARDB platform
LX2160ARDB is an evaluation board that supports LX2160A
family SoCs. This patch add base support for this board.
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Signed-off-by: Peng Ma <peng.ma@nxp.com>
Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
[PK: Sqaush patches from Yinbo Zhu, Peng Ma, Chuanhua Han
and re-arrange defconfig]
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
diff --git a/board/freescale/lx2160a/README b/board/freescale/lx2160a/README
new file mode 100644
index 0000000..618c40b
--- /dev/null
+++ b/board/freescale/lx2160a/README
@@ -0,0 +1,79 @@
+Overview
+--------
+The LX2160A Reference Design (RDB) is a high-performance computing,
+evaluation, and development platform that supports the QorIQ LX2160A
+Layerscape Architecture processor and its personalities.
+
+LX2160A SoC Overview
+--------------------------------------
+For details, please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
+
+LX2160ARDB board Overview
+----------------------
+DDR Memory
+ Two ports of 72-bits (8-bits ECC) DDR4.
+ Each port supports four chip-selects and two DIMM
+ connectors. Data rate upto 3.2 GT/s.
+
+SERDES ports
+ Thress serdes controllers (24 lanes)
+ Serdes1: Supports two USXGMII connectors, each connected through
+ Aquantia AQR107 phy, two 25GbE SFP+ modules connected through an Inphi
+ IN112525 phy and one 40 GbE QSFP+ module connected through an Inphi
+ CS4223 phy.
+
+ Serdes2: Supports one PCIe x4 (Gen1/2/3/4) connector, four SATA 3.0
+ connectors
+
+ Serdes3: Supports one PCIe x8 (Gen1/2/3/4) connector
+
+eSDHC
+ eSDHC1: Supports a SD connector for connecting SD cards
+ eSDHC2: Supports 128GB Micron MTFC128GAJAECE-IT eMMC
+
+Octal SPI (XSPI)
+ Supports two 64 MB onbpard octal SPI flash memories, one SPI emulator
+ for off-board emulation
+
+I2C All system devices on I2C1 multiplexed using PCA9547 multiplexer
+ Serial Ports
+
+USB 3.0
+ Two high speed USB 3.0 ports. First USB 3.0 port configured as
+ Host with Type-A connector, second USB 3.0 port configured as OTG
+ with micro-AB connector
+
+Serial Ports Two UART ports
+Ethernet Two RGMII interfaces
+Debug ARM JTAG support
+
+Booting Options
+---------------
+a) Flexspi boot
+b) SD boot
+
+Memory map for Flexspi flash
+----------------------------
+Image Flash Offset
+bl2_flexspi_nor.pbl (RCW+PBI+bl2.pbl) 0x00000000
+fip.bin (bl31 + bl33(u-boot) +
+ header for Secure-boot(secure-boot only)) 0x00100000
+Boot firmware Environment 0x00500000
+DDR PHY Firmware (fip_ddr_all.bin) 0x00800000
+DPAA2 MC Firmware 0x00A00000
+DPAA2 DPL 0x00D00000
+DPAA2 DPC 0x00E00000
+Kernel.itb 0x01000000
+
+Memory map for sd card
+----------------------------
+Image SD card Offset
+bl2_sd.pbl (RCW+PBI+bl2.pbl) 0x00008
+fip.bin (bl31 + bl33(u-boot) +
+ header for Secure-boot(secure-boot only)) 0x00800
+Boot firmware Environment 0x02800
+DDR PHY Firmware (fip_ddr_all.bin) 0x04000
+DPAA2 MC Firmware 0x05000
+DPAA2 DPL 0x06800
+DPAA2 DPC 0x07000
+Kernel.itb 0x08000