blob: a3df37d252dec572456c08e11fa3f004f1bfb9f5 [file] [log] [blame]
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2022 MediaTek Inc.
* Author: Sam Shih <sam.shih@mediatek.com>
*/
/dts-v1/;
#include "mt7988.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "mt7988-rfb";
compatible = "mediatek,mt7988-rfb", "mediatek,mt7988-sd-rfb";
chosen {
stdout-path = &uart0;
};
memory@40000000 {
device_type = "memory";
reg = <0 0x40000000 0 0x10000000>;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
&uart0 {
status = "okay";
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
status = "okay";
};
&eth {
status = "okay";
mediatek,gmac-id = <0>;
phy-mode = "usxgmii";
mediatek,switch = "mt7988";
fixed-link {
speed = <1000>;
full-duplex;
pause;
};
};
&pinctrl {
i2c1_pins: i2c1-pins {
mux {
function = "i2c";
groups = "i2c1_0";
};
};
pwm_pins: pwm-pins {
mux {
function = "pwm";
groups = "pwm0", "pwm1", "pwm2", "pwm3", "pwm4",
"pwm5", "pwm6", "pwm7";
};
};
spi0_pins: spi0-pins {
mux {
function = "spi";
groups = "spi0", "spi0_wp_hold";
};
};
mmc1_pins_default: mmc1default {
mux {
function = "flash";
groups = "emmc_45";
};
conf-cmd-dat {
pins = "SPI2_CSB", "SPI2_MISO", "SPI2_MOSI",
"SPI2_CLK", "SPI2_HOLD";
input-enable;
};
conf-clk {
pins = "SPI2_WP";
};
};
};
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm_pins>;
status = "okay";
};
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
must_tx;
enhance_timing;
dma_ext;
ipm_design;
support_quad;
tick_dly = <2>;
sample_sel = <0>;
spi_nand@0 {
compatible = "spi-nand";
reg = <0>;
spi-max-frequency = <52000000>;
};
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins_default>;
max-frequency = <52000000>;
bus-width = <4>;
cap-sd-highspeed;
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_3p3v>;
status = "okay";
};