global: Move remaining CONFIG_SYS_* to CFG_SYS_*
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do
not easily transition to Kconfig. In many cases they likely should come
from the device tree instead. Move these out of CONFIG namespace and in
to CFG namespace.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
diff --git a/drivers/bootcount/Kconfig b/drivers/bootcount/Kconfig
index 8d6424c..570252d 100644
--- a/drivers/bootcount/Kconfig
+++ b/drivers/bootcount/Kconfig
@@ -83,7 +83,7 @@
bool "Boot counter on I2C device"
help
Enable support for the bootcounter on an i2c (like RTC) device.
- CONFIG_SYS_I2C_RTC_ADDR = i2c chip address
+ CFG_SYS_I2C_RTC_ADDR = i2c chip address
CONFIG_SYS_BOOTCOUNT_ADDR = i2c addr which is used for
the bootcounter.
diff --git a/drivers/bootcount/bootcount_i2c.c b/drivers/bootcount/bootcount_i2c.c
index 496741d..b3ac67e 100644
--- a/drivers/bootcount/bootcount_i2c.c
+++ b/drivers/bootcount/bootcount_i2c.c
@@ -17,7 +17,7 @@
buf[0] = BC_MAGIC;
buf[1] = (a & 0xff);
- ret = i2c_write(CONFIG_SYS_I2C_RTC_ADDR, CONFIG_SYS_BOOTCOUNT_ADDR,
+ ret = i2c_write(CFG_SYS_I2C_RTC_ADDR, CONFIG_SYS_BOOTCOUNT_ADDR,
CONFIG_BOOTCOUNT_ALEN, buf, 2);
if (ret != 0)
puts("Error writing bootcount\n");
@@ -28,7 +28,7 @@
unsigned char buf[3];
int ret;
- ret = i2c_read(CONFIG_SYS_I2C_RTC_ADDR, CONFIG_SYS_BOOTCOUNT_ADDR,
+ ret = i2c_read(CFG_SYS_I2C_RTC_ADDR, CONFIG_SYS_BOOTCOUNT_ADDR,
CONFIG_BOOTCOUNT_ALEN, buf, 2);
if (ret != 0) {
puts("Error loading bootcount\n");
diff --git a/drivers/clk/at91/compat.c b/drivers/clk/at91/compat.c
index b2bfb52..2fdc2fb 100644
--- a/drivers/clk/at91/compat.c
+++ b/drivers/clk/at91/compat.c
@@ -150,7 +150,7 @@
static ulong at91_slow_clk_get_rate(struct clk *clk)
{
- return CONFIG_SYS_AT91_SLOW_CLOCK;
+ return CFG_SYS_AT91_SLOW_CLOCK;
}
static struct clk_ops at91_slow_clk_ops = {
diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig
index b79e99b..8fde77c 100644
--- a/drivers/core/Kconfig
+++ b/drivers/core/Kconfig
@@ -14,7 +14,7 @@
help
Enable driver model in SPL. You will need to provide a
suitable malloc() implementation. If you are not using the
- full malloc() enabled by CONFIG_SYS_SPL_MALLOC_START,
+ full malloc() enabled by CFG_SYS_SPL_MALLOC_START,
consider using CONFIG_SPL_SYS_MALLOC_SIMPLE. In that case you
must provide CONFIG_SPL_SYS_MALLOC_F_LEN to set the size.
In most cases driver model will only allocate a few uclasses
@@ -27,7 +27,7 @@
help
Enable driver model in TPL. You will need to provide a
suitable malloc() implementation. If you are not using the
- full malloc() enabled by CONFIG_SYS_SPL_MALLOC_START,
+ full malloc() enabled by CFG_SYS_SPL_MALLOC_START,
consider using CONFIG_TPL_SYS_MALLOC_SIMPLE. In that case you
must provide CONFIG_SPL_SYS_MALLOC_F_LEN to set the size.
In most cases driver model will only allocate a few uclasses
@@ -42,7 +42,7 @@
help
Enable driver model in VPL. You will need to provide a
suitable malloc() implementation. If you are not using the
- full malloc() enabled by CONFIG_SYS_SPL_MALLOC_START,
+ full malloc() enabled by CFG_SYS_SPL_MALLOC_START,
consider using CONFIG_SPL_SYS_MALLOC_SIMPLE.
config DM_WARN
diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c
index 4975dbb..cd33271 100644
--- a/drivers/ddr/fsl/main.c
+++ b/drivers/ddr/fsl/main.c
@@ -22,7 +22,7 @@
/*
* CFG_SYS_FSL_DDR_SDRAM_BASE_PHY is the physical address from the view
- * of DDR controllers. It is the same as CONFIG_SYS_DDR_SDRAM_BASE for
+ * of DDR controllers. It is the same as CFG_SYS_DDR_SDRAM_BASE for
* all Power SoCs. But it could be different for ARM SoCs. For example,
* fsl_lsch3 has a mapping mechanism to map DDR memory to ranges (in order) of
* 0x00_8000_0000 ~ 0x00_ffff_ffff
@@ -32,7 +32,7 @@
#ifdef CONFIG_MPC83xx
#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY CFG_SYS_SDRAM_BASE
#else
-#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY CFG_SYS_DDR_SDRAM_BASE
#endif
#endif
diff --git a/drivers/fpga/ACEX1K.c b/drivers/fpga/ACEX1K.c
index a1ff470..ca49ee4 100644
--- a/drivers/fpga/ACEX1K.c
+++ b/drivers/fpga/ACEX1K.c
@@ -24,8 +24,8 @@
#define CONFIG_FPGA_DELAY()
#endif
-#ifndef CONFIG_SYS_FPGA_WAIT
-#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/10 /* 100 ms */
+#ifndef CFG_SYS_FPGA_WAIT
+#define CFG_SYS_FPGA_WAIT CONFIG_SYS_HZ/10 /* 100 ms */
#endif
static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize);
@@ -138,7 +138,7 @@
ts = get_timer (0); /* get current time */
do {
CONFIG_FPGA_DELAY ();
- if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
+ if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for STATUS to go high.\n");
(*fn->abort) (cookie);
return FPGA_FAIL;
diff --git a/drivers/fpga/cyclon2.c b/drivers/fpga/cyclon2.c
index f264ff8..3eed461 100644
--- a/drivers/fpga/cyclon2.c
+++ b/drivers/fpga/cyclon2.c
@@ -22,8 +22,8 @@
#define CONFIG_FPGA_DELAY()
#endif
-#ifndef CONFIG_SYS_FPGA_WAIT
-#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ / 10 /* 100 ms */
+#ifndef CFG_SYS_FPGA_WAIT
+#define CFG_SYS_FPGA_WAIT CONFIG_SYS_HZ / 10 /* 100 ms */
#endif
static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize);
@@ -130,7 +130,7 @@
ts = get_timer(0); /* get current time */
do {
CONFIG_FPGA_DELAY();
- if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
+ if (get_timer(ts) > CFG_SYS_FPGA_WAIT) {
/* check the time */
puts("** Timeout waiting for STATUS to go high.\n");
(*fn->abort) (cookie);
diff --git a/drivers/fpga/spartan2.c b/drivers/fpga/spartan2.c
index f72dfde..57a4532 100644
--- a/drivers/fpga/spartan2.c
+++ b/drivers/fpga/spartan2.c
@@ -21,8 +21,8 @@
#define CONFIG_FPGA_DELAY()
#endif
-#ifndef CONFIG_SYS_FPGA_WAIT
-#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
+#ifndef CFG_SYS_FPGA_WAIT
+#define CFG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
#endif
static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize);
@@ -149,7 +149,7 @@
/* Now wait for INIT and BUSY to go high */
do {
CONFIG_FPGA_DELAY ();
- if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
+ if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for INIT to clear.\n");
(*fn->abort) (cookie); /* abort the burn */
return FPGA_FAIL;
@@ -182,7 +182,7 @@
CONFIG_FPGA_DELAY ();
(*fn->clk) (true, true, cookie); /* Assert the clock pin */
- if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
+ if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for BUSY to clear.\n");
(*fn->abort) (cookie); /* abort the burn */
return FPGA_FAIL;
@@ -214,7 +214,7 @@
CONFIG_FPGA_DELAY ();
(*fn->clk) (true, true, cookie); /* Assert the clock pin */
- if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
+ if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for DONE to clear.\n");
(*fn->abort) (cookie); /* abort the burn */
ret_val = FPGA_FAIL;
@@ -333,7 +333,7 @@
ts = get_timer (0); /* get current time */
do {
CONFIG_FPGA_DELAY ();
- if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
+ if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for INIT to start.\n");
return FPGA_FAIL;
}
@@ -347,7 +347,7 @@
/* Now wait for INIT to go high */
do {
CONFIG_FPGA_DELAY ();
- if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
+ if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for INIT to clear.\n");
return FPGA_FAIL;
}
@@ -404,7 +404,7 @@
putc ('*');
- if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
+ if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for DONE to clear.\n");
ret_val = FPGA_FAIL;
break;
diff --git a/drivers/fpga/spartan3.c b/drivers/fpga/spartan3.c
index b7a063a..fdec89b 100644
--- a/drivers/fpga/spartan3.c
+++ b/drivers/fpga/spartan3.c
@@ -26,8 +26,8 @@
#define CONFIG_FPGA_DELAY()
#endif
-#ifndef CONFIG_SYS_FPGA_WAIT
-#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
+#ifndef CFG_SYS_FPGA_WAIT
+#define CFG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
#endif
static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize);
@@ -154,7 +154,7 @@
/* Now wait for INIT and BUSY to go high */
do {
CONFIG_FPGA_DELAY ();
- if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
+ if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for INIT to clear.\n");
(*fn->abort) (cookie); /* abort the burn */
return FPGA_FAIL;
@@ -187,7 +187,7 @@
CONFIG_FPGA_DELAY ();
(*fn->clk) (true, true, cookie); /* Assert the clock pin */
- if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
+ if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for BUSY to clear.\n");
(*fn->abort) (cookie); /* abort the burn */
return FPGA_FAIL;
@@ -221,7 +221,7 @@
CONFIG_FPGA_DELAY ();
(*fn->clk) (true, true, cookie); /* Assert the clock pin */
- if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
+ if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for DONE to clear.\n");
(*fn->abort) (cookie); /* abort the burn */
ret_val = FPGA_FAIL;
@@ -340,7 +340,7 @@
ts = get_timer (0); /* get current time */
do {
CONFIG_FPGA_DELAY ();
- if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
+ if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for INIT to start.\n");
if (*fn->abort)
(*fn->abort) (cookie);
@@ -356,7 +356,7 @@
/* Now wait for INIT to go high */
do {
CONFIG_FPGA_DELAY ();
- if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
+ if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for INIT to clear.\n");
if (*fn->abort)
(*fn->abort) (cookie);
@@ -423,7 +423,7 @@
putc ('*');
- if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
+ if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for DONE to clear.\n");
ret_val = FPGA_FAIL;
break;
diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c
index 0d536f0..8871dea 100644
--- a/drivers/fpga/virtex2.c
+++ b/drivers/fpga/virtex2.c
@@ -49,8 +49,8 @@
* which yields 11.44 mS. So let's make it bigger in order to handle
* an XC2V1000, if anyone can ever get ahold of one.
*/
-#ifndef CONFIG_SYS_FPGA_WAIT_INIT
-#define CONFIG_SYS_FPGA_WAIT_INIT CONFIG_SYS_HZ / 2 /* 500 ms */
+#ifndef CFG_SYS_FPGA_WAIT_INIT
+#define CFG_SYS_FPGA_WAIT_INIT CONFIG_SYS_HZ / 2 /* 500 ms */
#endif
/*
@@ -58,15 +58,15 @@
* This is normally not necessary since for most reasonable configuration
* clock frequencies (i.e. 66 MHz or less), BUSY monitoring is unnecessary.
*/
-#ifndef CONFIG_SYS_FPGA_WAIT_BUSY
-#define CONFIG_SYS_FPGA_WAIT_BUSY CONFIG_SYS_HZ / 200 /* 5 ms*/
+#ifndef CFG_SYS_FPGA_WAIT_BUSY
+#define CFG_SYS_FPGA_WAIT_BUSY CONFIG_SYS_HZ / 200 /* 5 ms*/
#endif
/* Default timeout for waiting for FPGA to enter operational mode after
* configuration data has been written.
*/
-#ifndef CONFIG_SYS_FPGA_WAIT_CONFIG
-#define CONFIG_SYS_FPGA_WAIT_CONFIG CONFIG_SYS_HZ / 5 /* 200 ms */
+#ifndef CFG_SYS_FPGA_WAIT_CONFIG
+#define CFG_SYS_FPGA_WAIT_CONFIG CONFIG_SYS_HZ / 5 /* 200 ms */
#endif
static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize);
@@ -190,9 +190,9 @@
udelay(10);
ts = get_timer(0);
do {
- if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_INIT) {
+ if (get_timer(ts) > CFG_SYS_FPGA_WAIT_INIT) {
printf("%s:%d: ** Timeout after %d ticks waiting for INIT to assert.\n",
- __func__, __LINE__, CONFIG_SYS_FPGA_WAIT_INIT);
+ __func__, __LINE__, CFG_SYS_FPGA_WAIT_INIT);
(*fn->abort)(cookie);
return FPGA_FAIL;
}
@@ -209,9 +209,9 @@
ts = get_timer(0);
do {
CONFIG_FPGA_DELAY();
- if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_INIT) {
+ if (get_timer(ts) > CFG_SYS_FPGA_WAIT_INIT) {
printf("%s:%d: ** Timeout after %d ticks waiting for INIT to deassert.\n",
- __func__, __LINE__, CONFIG_SYS_FPGA_WAIT_INIT);
+ __func__, __LINE__, CFG_SYS_FPGA_WAIT_INIT);
(*fn->abort)(cookie);
return FPGA_FAIL;
}
@@ -260,9 +260,9 @@
break;
}
- if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_CONFIG) {
+ if (get_timer(ts) > CFG_SYS_FPGA_WAIT_CONFIG) {
printf("%s:%d: ** Timeout after %d ticks waiting for DONE to assert and INIT to deassert\n",
- __func__, __LINE__, CONFIG_SYS_FPGA_WAIT_CONFIG);
+ __func__, __LINE__, CFG_SYS_FPGA_WAIT_CONFIG);
(*fn->abort)(cookie);
ret_val = FPGA_FAIL;
break;
@@ -350,10 +350,10 @@
#ifdef CONFIG_SYS_FPGA_CHECK_BUSY
ts = get_timer(0);
while ((*fn->busy)(cookie)) {
- if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_BUSY) {
+ if (get_timer(ts) > CFG_SYS_FPGA_WAIT_BUSY) {
printf("%s:%d: ** Timeout after %d ticks waiting for BUSY to deassert\n",
__func__, __LINE__,
- CONFIG_SYS_FPGA_WAIT_BUSY);
+ CFG_SYS_FPGA_WAIT_BUSY);
(*fn->abort)(cookie);
return FPGA_FAIL;
}
diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c
index 0c83df4..53dd780 100644
--- a/drivers/fpga/zynqpl.c
+++ b/drivers/fpga/zynqpl.c
@@ -36,8 +36,8 @@
#define DEVCFG_MCTRL_RFIFO_FLUSH 0x00000002
#define DEVCFG_MCTRL_WFIFO_FLUSH 0x00000001
-#ifndef CONFIG_SYS_FPGA_WAIT
-#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
+#ifndef CFG_SYS_FPGA_WAIT
+#define CFG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
#endif
#ifndef CONFIG_SYS_FPGA_PROG_TIME
@@ -232,7 +232,7 @@
/* Polling the PCAP_INIT status for Reset */
ts = get_timer(0);
while (readl(&devcfg_base->status) & DEVCFG_STATUS_PCFG_INIT) {
- if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
+ if (get_timer(ts) > CFG_SYS_FPGA_WAIT) {
printf("%s: Timeout wait for INIT to clear\n",
__func__);
return FPGA_FAIL;
@@ -246,7 +246,7 @@
ts = get_timer(0);
while (!(readl(&devcfg_base->status) &
DEVCFG_STATUS_PCFG_INIT)) {
- if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
+ if (get_timer(ts) > CFG_SYS_FPGA_WAIT) {
printf("%s: Timeout wait for INIT to set\n",
__func__);
return FPGA_FAIL;
@@ -400,7 +400,7 @@
/* Check FPGA configuration completion */
ts = get_timer(0);
while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
- if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
+ if (get_timer(ts) > CFG_SYS_FPGA_WAIT) {
printf("%s: Timeout wait for FPGA to config\n",
__func__);
return FPGA_FAIL;
@@ -484,7 +484,7 @@
/* Check FPGA configuration completion */
ts = get_timer(0);
while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
- if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
+ if (get_timer(ts) > CFG_SYS_FPGA_WAIT) {
printf("%s: Timeout wait for FPGA to config\n",
__func__);
return FPGA_FAIL;
@@ -561,7 +561,7 @@
/* Check FPGA configuration completion */
ts = get_timer(0);
while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
- if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
+ if (get_timer(ts) > CFG_SYS_FPGA_WAIT) {
printf("%s: Timeout wait for FPGA to config\n",
__func__);
return FPGA_FAIL;
diff --git a/drivers/gpio/pca953x.c b/drivers/gpio/pca953x.c
index 2fd2996..b5ed352 100644
--- a/drivers/gpio/pca953x.c
+++ b/drivers/gpio/pca953x.c
@@ -14,8 +14,8 @@
#include <pca953x.h>
/* Default to an address that hopefully won't corrupt other i2c devices */
-#ifndef CONFIG_SYS_I2C_PCA953X_ADDR
-#define CONFIG_SYS_I2C_PCA953X_ADDR (~0)
+#ifndef CFG_SYS_I2C_PCA953X_ADDR
+#define CFG_SYS_I2C_PCA953X_ADDR (~0)
#endif
enum {
@@ -26,14 +26,14 @@
PCA953X_CMD_INVERT,
};
-#ifdef CONFIG_SYS_I2C_PCA953X_WIDTH
+#ifdef CFG_SYS_I2C_PCA953X_WIDTH
struct pca953x_chip_ngpio {
uint8_t chip;
uint8_t ngpio;
};
static struct pca953x_chip_ngpio pca953x_chip_ngpios[] =
- CONFIG_SYS_I2C_PCA953X_WIDTH;
+ CFG_SYS_I2C_PCA953X_WIDTH;
/*
* Determine the number of GPIO pins supported. If we don't know we assume
@@ -204,7 +204,7 @@
static int do_pca953x(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
- static uint8_t chip = CONFIG_SYS_I2C_PCA953X_ADDR;
+ static uint8_t chip = CFG_SYS_I2C_PCA953X_ADDR;
int ret = CMD_RET_USAGE, val;
ulong ul_arg2 = 0;
ulong ul_arg3 = 0;
diff --git a/drivers/gpio/tca642x.c b/drivers/gpio/tca642x.c
index 7f67f96..b07496e 100644
--- a/drivers/gpio/tca642x.c
+++ b/drivers/gpio/tca642x.c
@@ -52,7 +52,7 @@
int ret;
org_bus_num = i2c_get_bus_num();
- i2c_set_bus_num(CONFIG_SYS_I2C_TCA642X_BUS_NUM);
+ i2c_set_bus_num(CFG_SYS_I2C_TCA642X_BUS_NUM);
if (i2c_read(chip, addr, 1, (uint8_t *)&valw, 1)) {
printf("Could not read before writing\n");
@@ -76,7 +76,7 @@
int ret = 0;
org_bus_num = i2c_get_bus_num();
- i2c_set_bus_num(CONFIG_SYS_I2C_TCA642X_BUS_NUM);
+ i2c_set_bus_num(CFG_SYS_I2C_TCA642X_BUS_NUM);
if (i2c_read(chip, addr, 1, (u8 *)&valw, 1)) {
ret = -1;
goto error;
@@ -242,7 +242,7 @@
static int do_tca642x(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
- static uchar chip = CONFIG_SYS_I2C_TCA642X_ADDR;
+ static uchar chip = CFG_SYS_I2C_TCA642X_ADDR;
int ret = CMD_RET_USAGE, val;
int gpio_bank = 0;
uint8_t bank_shift;
diff --git a/drivers/i2c/davinci_i2c.c b/drivers/i2c/davinci_i2c.c
index ae17722..25ef937 100644
--- a/drivers/i2c/davinci_i2c.c
+++ b/drivers/i2c/davinci_i2c.c
@@ -91,7 +91,7 @@
psc = 2;
/* SCLL + SCLH */
- div = (CONFIG_SYS_HZ_CLOCK / ((psc + 1) * speed)) - 10;
+ div = (CFG_SYS_HZ_CLOCK / ((psc + 1) * speed)) - 10;
REG(&(i2c_base->i2c_psc)) = psc; /* 27MHz / (2 + 1) = 9MHz */
REG(&(i2c_base->i2c_scll)) = (div * 50) / 100; /* 50% Duty */
REG(&(i2c_base->i2c_sclh)) = div - REG(&(i2c_base->i2c_scll));
diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c
index edbcd83..187db92 100644
--- a/drivers/i2c/fsl_i2c.c
+++ b/drivers/i2c/fsl_i2c.c
@@ -41,7 +41,7 @@
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_M68K
-#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
+#define CONFIG_SYS_IMMR CFG_SYS_MBAR
#endif
#if !CONFIG_IS_ENABLED(DM_I2C)
diff --git a/drivers/i2c/i2c_core.c b/drivers/i2c/i2c_core.c
index c3f6a12..7f65db2 100644
--- a/drivers/i2c/i2c_core.c
+++ b/drivers/i2c/i2c_core.c
@@ -35,7 +35,7 @@
#if !defined(CONFIG_SYS_I2C_DIRECT_BUS)
struct i2c_bus_hose i2c_bus[CFG_SYS_NUM_I2C_BUSES] =
- CONFIG_SYS_I2C_BUSES;
+ CFG_SYS_I2C_BUSES;
#endif
DECLARE_GLOBAL_DATA_PTR;
@@ -114,7 +114,7 @@
/* Connect requested bus if behind muxes */
if (i2c_bus_tmp->next_hop[0].chip != 0) {
/* Set all muxes along the path to that bus */
- for (i = 0; i < CONFIG_SYS_I2C_MAX_HOPS; i++) {
+ for (i = 0; i < CFG_SYS_I2C_MAX_HOPS; i++) {
int ret;
if (i2c_bus_tmp->next_hop[i].chip == 0)
@@ -143,7 +143,7 @@
/* Disconnect current bus (turn off muxes if any) */
if ((i2c_bus_tmp->next_hop[0].chip != 0) &&
(I2C_ADAP->init_done != 0)) {
- i = CONFIG_SYS_I2C_MAX_HOPS;
+ i = CFG_SYS_I2C_MAX_HOPS;
do {
uint8_t chip;
int ret;
diff --git a/drivers/i2c/kona_i2c.c b/drivers/i2c/kona_i2c.c
index 4edcba2..b9b0ff1 100644
--- a/drivers/i2c/kona_i2c.c
+++ b/drivers/i2c/kona_i2c.c
@@ -129,7 +129,7 @@
#define DEF_DEVICE(num) \
{(void *)CONFIG_SYS_I2C_BASE##num, DEF_SPD, &std_cfg_table[DEF_SPD_ENUM]}
-static struct bcm_kona_i2c_dev g_i2c_devs[CONFIG_SYS_MAX_I2C_BUS] = {
+static struct bcm_kona_i2c_dev g_i2c_devs[CFG_SYS_MAX_I2C_BUS] = {
#ifdef CONFIG_SYS_I2C_BASE0
DEF_DEVICE(0),
#endif
diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c
index f48a4f2..a9c7d6e 100644
--- a/drivers/i2c/mvtwsi.c
+++ b/drivers/i2c/mvtwsi.c
@@ -42,7 +42,7 @@
#endif /* CONFIG_DM_I2C */
/*
- * On SUNXI, we get CONFIG_SYS_TCLK from this include, so we want to
+ * On SUNXI, we get CFG_SYS_TCLK from this include, so we want to
* always have it.
*/
#if CONFIG_IS_ENABLED(DM_I2C) && defined(CONFIG_ARCH_SUNXI)
@@ -427,9 +427,9 @@
static uint twsi_calc_freq(const int n, const int m)
{
#ifdef CONFIG_ARCH_SUNXI
- return CONFIG_SYS_TCLK / (10 * (m + 1) * (1 << n));
+ return CFG_SYS_TCLK / (10 * (m + 1) * (1 << n));
#else
- return CONFIG_SYS_TCLK / (10 * (m + 1) * (2 << n));
+ return CFG_SYS_TCLK / (10 * (m + 1) * (2 << n));
#endif
}
diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index f80ff53..9a1599d 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -39,8 +39,8 @@
#define VF610_I2C_REGSHIFT 0
#define I2C_EARLY_INIT_INDEX 0
-#ifdef CONFIG_SYS_I2C_IFDR_DIV
-#define I2C_IFDR_DIV_CONSERVATIVE CONFIG_SYS_I2C_IFDR_DIV
+#ifdef CFG_SYS_I2C_IFDR_DIV
+#define I2C_IFDR_DIV_CONSERVATIVE CFG_SYS_I2C_IFDR_DIV
#else
#define I2C_IFDR_DIV_CONSERVATIVE 0x7e
#endif
diff --git a/drivers/misc/fsl_ifc.c b/drivers/misc/fsl_ifc.c
index 8fdaacd..58b0058 100644
--- a/drivers/misc/fsl_ifc.c
+++ b/drivers/misc/fsl_ifc.c
@@ -12,37 +12,37 @@
struct ifc_regs ifc_cfg_default_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
{
"cs0",
-#if defined(CONFIG_SYS_CSPR0) && defined(CONFIG_SYS_CSOR0)
- CONFIG_SYS_CSPR0,
-#ifdef CONFIG_SYS_CSPR0_EXT
- CONFIG_SYS_CSPR0_EXT,
+#if defined(CFG_SYS_CSPR0) && defined(CFG_SYS_CSOR0)
+ CFG_SYS_CSPR0,
+#ifdef CFG_SYS_CSPR0_EXT
+ CFG_SYS_CSPR0_EXT,
#else
0,
#endif
-#ifdef CONFIG_SYS_AMASK0
- CONFIG_SYS_AMASK0,
+#ifdef CFG_SYS_AMASK0
+ CFG_SYS_AMASK0,
#else
0,
#endif
- CONFIG_SYS_CSOR0,
+ CFG_SYS_CSOR0,
{
- CONFIG_SYS_CS0_FTIM0,
- CONFIG_SYS_CS0_FTIM1,
- CONFIG_SYS_CS0_FTIM2,
- CONFIG_SYS_CS0_FTIM3,
+ CFG_SYS_CS0_FTIM0,
+ CFG_SYS_CS0_FTIM1,
+ CFG_SYS_CS0_FTIM2,
+ CFG_SYS_CS0_FTIM3,
},
-#ifdef CONFIG_SYS_CSOR0_EXT
- CONFIG_SYS_CSOR0_EXT,
+#ifdef CFG_SYS_CSOR0_EXT
+ CFG_SYS_CSOR0_EXT,
#else
0,
#endif
-#ifdef CONFIG_SYS_CSPR0_FINAL
- CONFIG_SYS_CSPR0_FINAL,
+#ifdef CFG_SYS_CSPR0_FINAL
+ CFG_SYS_CSPR0_FINAL,
#else
0,
#endif
-#ifdef CONFIG_SYS_AMASK0_FINAL
- CONFIG_SYS_AMASK0_FINAL,
+#ifdef CFG_SYS_AMASK0_FINAL
+ CFG_SYS_AMASK0_FINAL,
#else
0,
#endif
@@ -52,37 +52,37 @@
#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 2
{
"cs1",
-#if defined(CONFIG_SYS_CSPR1) && defined(CONFIG_SYS_CSOR1)
- CONFIG_SYS_CSPR1,
-#ifdef CONFIG_SYS_CSPR1_EXT
- CONFIG_SYS_CSPR1_EXT,
+#if defined(CFG_SYS_CSPR1) && defined(CFG_SYS_CSOR1)
+ CFG_SYS_CSPR1,
+#ifdef CFG_SYS_CSPR1_EXT
+ CFG_SYS_CSPR1_EXT,
#else
0,
#endif
-#ifdef CONFIG_SYS_AMASK1
- CONFIG_SYS_AMASK1,
+#ifdef CFG_SYS_AMASK1
+ CFG_SYS_AMASK1,
#else
0,
#endif
- CONFIG_SYS_CSOR1,
+ CFG_SYS_CSOR1,
{
- CONFIG_SYS_CS1_FTIM0,
- CONFIG_SYS_CS1_FTIM1,
- CONFIG_SYS_CS1_FTIM2,
- CONFIG_SYS_CS1_FTIM3,
+ CFG_SYS_CS1_FTIM0,
+ CFG_SYS_CS1_FTIM1,
+ CFG_SYS_CS1_FTIM2,
+ CFG_SYS_CS1_FTIM3,
},
-#ifdef CONFIG_SYS_CSOR1_EXT
- CONFIG_SYS_CSOR1_EXT,
+#ifdef CFG_SYS_CSOR1_EXT
+ CFG_SYS_CSOR1_EXT,
#else
0,
#endif
-#ifdef CONFIG_SYS_CSPR1_FINAL
- CONFIG_SYS_CSPR1_FINAL,
+#ifdef CFG_SYS_CSPR1_FINAL
+ CFG_SYS_CSPR1_FINAL,
#else
0,
#endif
-#ifdef CONFIG_SYS_AMASK1_FINAL
- CONFIG_SYS_AMASK1_FINAL,
+#ifdef CFG_SYS_AMASK1_FINAL
+ CFG_SYS_AMASK1_FINAL,
#else
0,
#endif
@@ -93,37 +93,37 @@
#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 3
{
"cs2",
-#if defined(CONFIG_SYS_CSPR2) && defined(CONFIG_SYS_CSOR2)
- CONFIG_SYS_CSPR2,
-#ifdef CONFIG_SYS_CSPR2_EXT
- CONFIG_SYS_CSPR2_EXT,
+#if defined(CFG_SYS_CSPR2) && defined(CFG_SYS_CSOR2)
+ CFG_SYS_CSPR2,
+#ifdef CFG_SYS_CSPR2_EXT
+ CFG_SYS_CSPR2_EXT,
#else
0,
#endif
-#ifdef CONFIG_SYS_AMASK2
- CONFIG_SYS_AMASK2,
+#ifdef CFG_SYS_AMASK2
+ CFG_SYS_AMASK2,
#else
0,
#endif
- CONFIG_SYS_CSOR2,
+ CFG_SYS_CSOR2,
{
- CONFIG_SYS_CS2_FTIM0,
- CONFIG_SYS_CS2_FTIM1,
- CONFIG_SYS_CS2_FTIM2,
- CONFIG_SYS_CS2_FTIM3,
+ CFG_SYS_CS2_FTIM0,
+ CFG_SYS_CS2_FTIM1,
+ CFG_SYS_CS2_FTIM2,
+ CFG_SYS_CS2_FTIM3,
},
-#ifdef CONFIG_SYS_CSOR2_EXT
- CONFIG_SYS_CSOR2_EXT,
+#ifdef CFG_SYS_CSOR2_EXT
+ CFG_SYS_CSOR2_EXT,
#else
0,
#endif
-#ifdef CONFIG_SYS_CSPR2_FINAL
- CONFIG_SYS_CSPR2_FINAL,
+#ifdef CFG_SYS_CSPR2_FINAL
+ CFG_SYS_CSPR2_FINAL,
#else
0,
#endif
-#ifdef CONFIG_SYS_AMASK2_FINAL
- CONFIG_SYS_AMASK2_FINAL,
+#ifdef CFG_SYS_AMASK2_FINAL
+ CFG_SYS_AMASK2_FINAL,
#else
0,
#endif
@@ -134,37 +134,37 @@
#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 4
{
"cs3",
-#if defined(CONFIG_SYS_CSPR3) && defined(CONFIG_SYS_CSOR3)
- CONFIG_SYS_CSPR3,
-#ifdef CONFIG_SYS_CSPR3_EXT
- CONFIG_SYS_CSPR3_EXT,
+#if defined(CFG_SYS_CSPR3) && defined(CFG_SYS_CSOR3)
+ CFG_SYS_CSPR3,
+#ifdef CFG_SYS_CSPR3_EXT
+ CFG_SYS_CSPR3_EXT,
#else
0,
#endif
-#ifdef CONFIG_SYS_AMASK3
- CONFIG_SYS_AMASK3,
+#ifdef CFG_SYS_AMASK3
+ CFG_SYS_AMASK3,
#else
0,
#endif
- CONFIG_SYS_CSOR3,
+ CFG_SYS_CSOR3,
{
- CONFIG_SYS_CS3_FTIM0,
- CONFIG_SYS_CS3_FTIM1,
- CONFIG_SYS_CS3_FTIM2,
- CONFIG_SYS_CS3_FTIM3,
+ CFG_SYS_CS3_FTIM0,
+ CFG_SYS_CS3_FTIM1,
+ CFG_SYS_CS3_FTIM2,
+ CFG_SYS_CS3_FTIM3,
},
-#ifdef CONFIG_SYS_CSOR3_EXT
- CONFIG_SYS_CSOR3_EXT,
+#ifdef CFG_SYS_CSOR3_EXT
+ CFG_SYS_CSOR3_EXT,
#else
0,
#endif
-#ifdef CONFIG_SYS_CSPR3_FINAL
- CONFIG_SYS_CSPR3_FINAL,
+#ifdef CFG_SYS_CSPR3_FINAL
+ CFG_SYS_CSPR3_FINAL,
#else
0,
#endif
-#ifdef CONFIG_SYS_AMASK3_FINAL
- CONFIG_SYS_AMASK3_FINAL,
+#ifdef CFG_SYS_AMASK3_FINAL
+ CFG_SYS_AMASK3_FINAL,
#else
0,
#endif
@@ -175,37 +175,37 @@
#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 5
{
"cs4",
-#if defined(CONFIG_SYS_CSPR4) && defined(CONFIG_SYS_CSOR4)
- CONFIG_SYS_CSPR4,
-#ifdef CONFIG_SYS_CSPR4_EXT
- CONFIG_SYS_CSPR4_EXT,
+#if defined(CFG_SYS_CSPR4) && defined(CFG_SYS_CSOR4)
+ CFG_SYS_CSPR4,
+#ifdef CFG_SYS_CSPR4_EXT
+ CFG_SYS_CSPR4_EXT,
#else
0,
#endif
-#ifdef CONFIG_SYS_AMASK4
- CONFIG_SYS_AMASK4,
+#ifdef CFG_SYS_AMASK4
+ CFG_SYS_AMASK4,
#else
0,
#endif
- CONFIG_SYS_CSOR4,
+ CFG_SYS_CSOR4,
{
- CONFIG_SYS_CS4_FTIM0,
- CONFIG_SYS_CS4_FTIM1,
- CONFIG_SYS_CS4_FTIM2,
- CONFIG_SYS_CS4_FTIM3,
+ CFG_SYS_CS4_FTIM0,
+ CFG_SYS_CS4_FTIM1,
+ CFG_SYS_CS4_FTIM2,
+ CFG_SYS_CS4_FTIM3,
},
-#ifdef CONFIG_SYS_CSOR4_EXT
- CONFIG_SYS_CSOR4_EXT,
+#ifdef CFG_SYS_CSOR4_EXT
+ CFG_SYS_CSOR4_EXT,
#else
0,
#endif
-#ifdef CONFIG_SYS_CSPR4_FINAL
- CONFIG_SYS_CSPR4_FINAL,
+#ifdef CFG_SYS_CSPR4_FINAL
+ CFG_SYS_CSPR4_FINAL,
#else
0,
#endif
-#ifdef CONFIG_SYS_AMASK4_FINAL
- CONFIG_SYS_AMASK4_FINAL,
+#ifdef CFG_SYS_AMASK4_FINAL
+ CFG_SYS_AMASK4_FINAL,
#else
0,
#endif
@@ -257,37 +257,37 @@
#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 7
{
"cs6",
-#if defined(CONFIG_SYS_CSPR6) && defined(CONFIG_SYS_CSOR6)
- CONFIG_SYS_CSPR6,
-#ifdef CONFIG_SYS_CSPR6_EXT
- CONFIG_SYS_CSPR6_EXT,
+#if defined(CFG_SYS_CSPR6) && defined(CFG_SYS_CSOR6)
+ CFG_SYS_CSPR6,
+#ifdef CFG_SYS_CSPR6_EXT
+ CFG_SYS_CSPR6_EXT,
#else
0,
#endif
-#ifdef CONFIG_SYS_AMASK6
- CONFIG_SYS_AMASK6,
+#ifdef CFG_SYS_AMASK6
+ CFG_SYS_AMASK6,
#else
0,
#endif
- CONFIG_SYS_CSOR6,
+ CFG_SYS_CSOR6,
{
- CONFIG_SYS_CS6_FTIM0,
- CONFIG_SYS_CS6_FTIM1,
- CONFIG_SYS_CS6_FTIM2,
- CONFIG_SYS_CS6_FTIM3,
+ CFG_SYS_CS6_FTIM0,
+ CFG_SYS_CS6_FTIM1,
+ CFG_SYS_CS6_FTIM2,
+ CFG_SYS_CS6_FTIM3,
},
-#ifdef CONFIG_SYS_CSOR6_EXT
- CONFIG_SYS_CSOR6_EXT,
+#ifdef CFG_SYS_CSOR6_EXT
+ CFG_SYS_CSOR6_EXT,
#else
0,
#endif
-#ifdef CONFIG_SYS_CSPR6_FINAL
- CONFIG_SYS_CSPR6_FINAL,
+#ifdef CFG_SYS_CSPR6_FINAL
+ CFG_SYS_CSPR6_FINAL,
#else
0,
#endif
-#ifdef CONFIG_SYS_AMASK6_FINAL
- CONFIG_SYS_AMASK6_FINAL,
+#ifdef CFG_SYS_AMASK6_FINAL
+ CFG_SYS_AMASK6_FINAL,
#else
0,
#endif
@@ -298,37 +298,37 @@
#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 8
{
"cs7",
-#if defined(CONFIG_SYS_CSPR7) && defined(CONFIG_SYS_CSOR7)
- CONFIG_SYS_CSPR7,
-#ifdef CONFIG_SYS_CSPR7_EXT
- CONFIG_SYS_CSPR7_EXT,
+#if defined(CFG_SYS_CSPR7) && defined(CFG_SYS_CSOR7)
+ CFG_SYS_CSPR7,
+#ifdef CFG_SYS_CSPR7_EXT
+ CFG_SYS_CSPR7_EXT,
#else
0,
#endif
-#ifdef CONFIG_SYS_AMASK7
- CONFIG_SYS_AMASK7,
+#ifdef CFG_SYS_AMASK7
+ CFG_SYS_AMASK7,
#else
0,
#endif
- CONFIG_SYS_CSOR7,
-#ifdef CONFIG_SYS_CSOR7_EXT
- CONFIG_SYS_CSOR7_EXT,
+ CFG_SYS_CSOR7,
+#ifdef CFG_SYS_CSOR7_EXT
+ CFG_SYS_CSOR7_EXT,
#else
0,
#endif
{
- CONFIG_SYS_CS7_FTIM0,
- CONFIG_SYS_CS7_FTIM1,
- CONFIG_SYS_CS7_FTIM2,
- CONFIG_SYS_CS7_FTIM3,
+ CFG_SYS_CS7_FTIM0,
+ CFG_SYS_CS7_FTIM1,
+ CFG_SYS_CS7_FTIM2,
+ CFG_SYS_CS7_FTIM3,
},
-#ifdef CONFIG_SYS_CSPR7_FINAL
- CONFIG_SYS_CSPR7_FINAL,
+#ifdef CFG_SYS_CSPR7_FINAL
+ CFG_SYS_CSPR7_FINAL,
#else
0,
#endif
-#ifdef CONFIG_SYS_AMASK7_FINAL
- CONFIG_SYS_AMASK7_FINAL,
+#ifdef CFG_SYS_AMASK7_FINAL
+ CFG_SYS_AMASK7_FINAL,
#else
0,
#endif
@@ -412,91 +412,91 @@
#else
void init_early_memctl_regs(void)
{
-#if defined(CONFIG_SYS_CSPR0) && defined(CONFIG_SYS_CSOR0)
- set_ifc_ftim(IFC_CS0, IFC_FTIM0, CONFIG_SYS_CS0_FTIM0);
- set_ifc_ftim(IFC_CS0, IFC_FTIM1, CONFIG_SYS_CS0_FTIM1);
- set_ifc_ftim(IFC_CS0, IFC_FTIM2, CONFIG_SYS_CS0_FTIM2);
- set_ifc_ftim(IFC_CS0, IFC_FTIM3, CONFIG_SYS_CS0_FTIM3);
+#if defined(CFG_SYS_CSPR0) && defined(CFG_SYS_CSOR0)
+ set_ifc_ftim(IFC_CS0, IFC_FTIM0, CFG_SYS_CS0_FTIM0);
+ set_ifc_ftim(IFC_CS0, IFC_FTIM1, CFG_SYS_CS0_FTIM1);
+ set_ifc_ftim(IFC_CS0, IFC_FTIM2, CFG_SYS_CS0_FTIM2);
+ set_ifc_ftim(IFC_CS0, IFC_FTIM3, CFG_SYS_CS0_FTIM3);
#ifndef CONFIG_A003399_NOR_WORKAROUND
-#ifdef CONFIG_SYS_CSPR0_EXT
- set_ifc_cspr_ext(IFC_CS0, CONFIG_SYS_CSPR0_EXT);
+#ifdef CFG_SYS_CSPR0_EXT
+ set_ifc_cspr_ext(IFC_CS0, CFG_SYS_CSPR0_EXT);
#endif
-#ifdef CONFIG_SYS_CSOR0_EXT
- set_ifc_csor_ext(IFC_CS0, CONFIG_SYS_CSOR0_EXT);
+#ifdef CFG_SYS_CSOR0_EXT
+ set_ifc_csor_ext(IFC_CS0, CFG_SYS_CSOR0_EXT);
#endif
- set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0);
- set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0);
- set_ifc_csor(IFC_CS0, CONFIG_SYS_CSOR0);
+ set_ifc_cspr(IFC_CS0, CFG_SYS_CSPR0);
+ set_ifc_amask(IFC_CS0, CFG_SYS_AMASK0);
+ set_ifc_csor(IFC_CS0, CFG_SYS_CSOR0);
#endif
#endif
-#ifdef CONFIG_SYS_CSPR1_EXT
- set_ifc_cspr_ext(IFC_CS1, CONFIG_SYS_CSPR1_EXT);
+#ifdef CFG_SYS_CSPR1_EXT
+ set_ifc_cspr_ext(IFC_CS1, CFG_SYS_CSPR1_EXT);
#endif
-#ifdef CONFIG_SYS_CSOR1_EXT
- set_ifc_csor_ext(IFC_CS1, CONFIG_SYS_CSOR1_EXT);
+#ifdef CFG_SYS_CSOR1_EXT
+ set_ifc_csor_ext(IFC_CS1, CFG_SYS_CSOR1_EXT);
#endif
-#if defined(CONFIG_SYS_CSPR1) && defined(CONFIG_SYS_CSOR1)
- set_ifc_ftim(IFC_CS1, IFC_FTIM0, CONFIG_SYS_CS1_FTIM0);
- set_ifc_ftim(IFC_CS1, IFC_FTIM1, CONFIG_SYS_CS1_FTIM1);
- set_ifc_ftim(IFC_CS1, IFC_FTIM2, CONFIG_SYS_CS1_FTIM2);
- set_ifc_ftim(IFC_CS1, IFC_FTIM3, CONFIG_SYS_CS1_FTIM3);
+#if defined(CFG_SYS_CSPR1) && defined(CFG_SYS_CSOR1)
+ set_ifc_ftim(IFC_CS1, IFC_FTIM0, CFG_SYS_CS1_FTIM0);
+ set_ifc_ftim(IFC_CS1, IFC_FTIM1, CFG_SYS_CS1_FTIM1);
+ set_ifc_ftim(IFC_CS1, IFC_FTIM2, CFG_SYS_CS1_FTIM2);
+ set_ifc_ftim(IFC_CS1, IFC_FTIM3, CFG_SYS_CS1_FTIM3);
- set_ifc_csor(IFC_CS1, CONFIG_SYS_CSOR1);
- set_ifc_amask(IFC_CS1, CONFIG_SYS_AMASK1);
- set_ifc_cspr(IFC_CS1, CONFIG_SYS_CSPR1);
+ set_ifc_csor(IFC_CS1, CFG_SYS_CSOR1);
+ set_ifc_amask(IFC_CS1, CFG_SYS_AMASK1);
+ set_ifc_cspr(IFC_CS1, CFG_SYS_CSPR1);
#endif
-#ifdef CONFIG_SYS_CSPR2_EXT
- set_ifc_cspr_ext(IFC_CS2, CONFIG_SYS_CSPR2_EXT);
+#ifdef CFG_SYS_CSPR2_EXT
+ set_ifc_cspr_ext(IFC_CS2, CFG_SYS_CSPR2_EXT);
#endif
-#ifdef CONFIG_SYS_CSOR2_EXT
- set_ifc_csor_ext(IFC_CS2, CONFIG_SYS_CSOR2_EXT);
+#ifdef CFG_SYS_CSOR2_EXT
+ set_ifc_csor_ext(IFC_CS2, CFG_SYS_CSOR2_EXT);
#endif
-#if defined(CONFIG_SYS_CSPR2) && defined(CONFIG_SYS_CSOR2)
- set_ifc_ftim(IFC_CS2, IFC_FTIM0, CONFIG_SYS_CS2_FTIM0);
- set_ifc_ftim(IFC_CS2, IFC_FTIM1, CONFIG_SYS_CS2_FTIM1);
- set_ifc_ftim(IFC_CS2, IFC_FTIM2, CONFIG_SYS_CS2_FTIM2);
- set_ifc_ftim(IFC_CS2, IFC_FTIM3, CONFIG_SYS_CS2_FTIM3);
+#if defined(CFG_SYS_CSPR2) && defined(CFG_SYS_CSOR2)
+ set_ifc_ftim(IFC_CS2, IFC_FTIM0, CFG_SYS_CS2_FTIM0);
+ set_ifc_ftim(IFC_CS2, IFC_FTIM1, CFG_SYS_CS2_FTIM1);
+ set_ifc_ftim(IFC_CS2, IFC_FTIM2, CFG_SYS_CS2_FTIM2);
+ set_ifc_ftim(IFC_CS2, IFC_FTIM3, CFG_SYS_CS2_FTIM3);
- set_ifc_csor(IFC_CS2, CONFIG_SYS_CSOR2);
- set_ifc_amask(IFC_CS2, CONFIG_SYS_AMASK2);
- set_ifc_cspr(IFC_CS2, CONFIG_SYS_CSPR2);
+ set_ifc_csor(IFC_CS2, CFG_SYS_CSOR2);
+ set_ifc_amask(IFC_CS2, CFG_SYS_AMASK2);
+ set_ifc_cspr(IFC_CS2, CFG_SYS_CSPR2);
#endif
-#ifdef CONFIG_SYS_CSPR3_EXT
- set_ifc_cspr_ext(IFC_CS3, CONFIG_SYS_CSPR3_EXT);
+#ifdef CFG_SYS_CSPR3_EXT
+ set_ifc_cspr_ext(IFC_CS3, CFG_SYS_CSPR3_EXT);
#endif
-#ifdef CONFIG_SYS_CSOR3_EXT
- set_ifc_csor_ext(IFC_CS3, CONFIG_SYS_CSOR3_EXT);
+#ifdef CFG_SYS_CSOR3_EXT
+ set_ifc_csor_ext(IFC_CS3, CFG_SYS_CSOR3_EXT);
#endif
-#if defined(CONFIG_SYS_CSPR3) && defined(CONFIG_SYS_CSOR3)
- set_ifc_ftim(IFC_CS3, IFC_FTIM0, CONFIG_SYS_CS3_FTIM0);
- set_ifc_ftim(IFC_CS3, IFC_FTIM1, CONFIG_SYS_CS3_FTIM1);
- set_ifc_ftim(IFC_CS3, IFC_FTIM2, CONFIG_SYS_CS3_FTIM2);
- set_ifc_ftim(IFC_CS3, IFC_FTIM3, CONFIG_SYS_CS3_FTIM3);
+#if defined(CFG_SYS_CSPR3) && defined(CFG_SYS_CSOR3)
+ set_ifc_ftim(IFC_CS3, IFC_FTIM0, CFG_SYS_CS3_FTIM0);
+ set_ifc_ftim(IFC_CS3, IFC_FTIM1, CFG_SYS_CS3_FTIM1);
+ set_ifc_ftim(IFC_CS3, IFC_FTIM2, CFG_SYS_CS3_FTIM2);
+ set_ifc_ftim(IFC_CS3, IFC_FTIM3, CFG_SYS_CS3_FTIM3);
- set_ifc_cspr(IFC_CS3, CONFIG_SYS_CSPR3);
- set_ifc_amask(IFC_CS3, CONFIG_SYS_AMASK3);
- set_ifc_csor(IFC_CS3, CONFIG_SYS_CSOR3);
+ set_ifc_cspr(IFC_CS3, CFG_SYS_CSPR3);
+ set_ifc_amask(IFC_CS3, CFG_SYS_AMASK3);
+ set_ifc_csor(IFC_CS3, CFG_SYS_CSOR3);
#endif
-#ifdef CONFIG_SYS_CSPR4_EXT
- set_ifc_cspr_ext(IFC_CS4, CONFIG_SYS_CSPR4_EXT);
+#ifdef CFG_SYS_CSPR4_EXT
+ set_ifc_cspr_ext(IFC_CS4, CFG_SYS_CSPR4_EXT);
#endif
-#ifdef CONFIG_SYS_CSOR4_EXT
- set_ifc_csor_ext(IFC_CS4, CONFIG_SYS_CSOR4_EXT);
+#ifdef CFG_SYS_CSOR4_EXT
+ set_ifc_csor_ext(IFC_CS4, CFG_SYS_CSOR4_EXT);
#endif
-#if defined(CONFIG_SYS_CSPR4) && defined(CONFIG_SYS_CSOR4)
- set_ifc_ftim(IFC_CS4, IFC_FTIM0, CONFIG_SYS_CS4_FTIM0);
- set_ifc_ftim(IFC_CS4, IFC_FTIM1, CONFIG_SYS_CS4_FTIM1);
- set_ifc_ftim(IFC_CS4, IFC_FTIM2, CONFIG_SYS_CS4_FTIM2);
- set_ifc_ftim(IFC_CS4, IFC_FTIM3, CONFIG_SYS_CS4_FTIM3);
+#if defined(CFG_SYS_CSPR4) && defined(CFG_SYS_CSOR4)
+ set_ifc_ftim(IFC_CS4, IFC_FTIM0, CFG_SYS_CS4_FTIM0);
+ set_ifc_ftim(IFC_CS4, IFC_FTIM1, CFG_SYS_CS4_FTIM1);
+ set_ifc_ftim(IFC_CS4, IFC_FTIM2, CFG_SYS_CS4_FTIM2);
+ set_ifc_ftim(IFC_CS4, IFC_FTIM3, CFG_SYS_CS4_FTIM3);
- set_ifc_cspr(IFC_CS4, CONFIG_SYS_CSPR4);
- set_ifc_amask(IFC_CS4, CONFIG_SYS_AMASK4);
- set_ifc_csor(IFC_CS4, CONFIG_SYS_CSOR4);
+ set_ifc_cspr(IFC_CS4, CFG_SYS_CSPR4);
+ set_ifc_amask(IFC_CS4, CFG_SYS_AMASK4);
+ set_ifc_csor(IFC_CS4, CFG_SYS_CSOR4);
#endif
#ifdef CONFIG_SYS_CSPR5_EXT
@@ -516,66 +516,66 @@
set_ifc_csor(IFC_CS5, CONFIG_SYS_CSOR5);
#endif
-#ifdef CONFIG_SYS_CSPR6_EXT
- set_ifc_cspr_ext(IFC_CS6, CONFIG_SYS_CSPR6_EXT);
+#ifdef CFG_SYS_CSPR6_EXT
+ set_ifc_cspr_ext(IFC_CS6, CFG_SYS_CSPR6_EXT);
#endif
-#ifdef CONFIG_SYS_CSOR6_EXT
- set_ifc_csor_ext(IFC_CS6, CONFIG_SYS_CSOR6_EXT);
+#ifdef CFG_SYS_CSOR6_EXT
+ set_ifc_csor_ext(IFC_CS6, CFG_SYS_CSOR6_EXT);
#endif
-#if defined(CONFIG_SYS_CSPR6) && defined(CONFIG_SYS_CSOR6)
- set_ifc_ftim(IFC_CS6, IFC_FTIM0, CONFIG_SYS_CS6_FTIM0);
- set_ifc_ftim(IFC_CS6, IFC_FTIM1, CONFIG_SYS_CS6_FTIM1);
- set_ifc_ftim(IFC_CS6, IFC_FTIM2, CONFIG_SYS_CS6_FTIM2);
- set_ifc_ftim(IFC_CS6, IFC_FTIM3, CONFIG_SYS_CS6_FTIM3);
+#if defined(CFG_SYS_CSPR6) && defined(CFG_SYS_CSOR6)
+ set_ifc_ftim(IFC_CS6, IFC_FTIM0, CFG_SYS_CS6_FTIM0);
+ set_ifc_ftim(IFC_CS6, IFC_FTIM1, CFG_SYS_CS6_FTIM1);
+ set_ifc_ftim(IFC_CS6, IFC_FTIM2, CFG_SYS_CS6_FTIM2);
+ set_ifc_ftim(IFC_CS6, IFC_FTIM3, CFG_SYS_CS6_FTIM3);
- set_ifc_cspr(IFC_CS6, CONFIG_SYS_CSPR6);
- set_ifc_amask(IFC_CS6, CONFIG_SYS_AMASK6);
- set_ifc_csor(IFC_CS6, CONFIG_SYS_CSOR6);
+ set_ifc_cspr(IFC_CS6, CFG_SYS_CSPR6);
+ set_ifc_amask(IFC_CS6, CFG_SYS_AMASK6);
+ set_ifc_csor(IFC_CS6, CFG_SYS_CSOR6);
#endif
-#ifdef CONFIG_SYS_CSPR7_EXT
- set_ifc_cspr_ext(IFC_CS7, CONFIG_SYS_CSPR7_EXT);
+#ifdef CFG_SYS_CSPR7_EXT
+ set_ifc_cspr_ext(IFC_CS7, CFG_SYS_CSPR7_EXT);
#endif
-#ifdef CONFIG_SYS_CSOR7_EXT
- set_ifc_csor_ext(IFC_CS7, CONFIG_SYS_CSOR7_EXT);
+#ifdef CFG_SYS_CSOR7_EXT
+ set_ifc_csor_ext(IFC_CS7, CFG_SYS_CSOR7_EXT);
#endif
-#if defined(CONFIG_SYS_CSPR7) && defined(CONFIG_SYS_CSOR7)
- set_ifc_ftim(IFC_CS7, IFC_FTIM0, CONFIG_SYS_CS7_FTIM0);
- set_ifc_ftim(IFC_CS7, IFC_FTIM1, CONFIG_SYS_CS7_FTIM1);
- set_ifc_ftim(IFC_CS7, IFC_FTIM2, CONFIG_SYS_CS7_FTIM2);
- set_ifc_ftim(IFC_CS7, IFC_FTIM3, CONFIG_SYS_CS7_FTIM3);
+#if defined(CFG_SYS_CSPR7) && defined(CFG_SYS_CSOR7)
+ set_ifc_ftim(IFC_CS7, IFC_FTIM0, CFG_SYS_CS7_FTIM0);
+ set_ifc_ftim(IFC_CS7, IFC_FTIM1, CFG_SYS_CS7_FTIM1);
+ set_ifc_ftim(IFC_CS7, IFC_FTIM2, CFG_SYS_CS7_FTIM2);
+ set_ifc_ftim(IFC_CS7, IFC_FTIM3, CFG_SYS_CS7_FTIM3);
- set_ifc_cspr(IFC_CS7, CONFIG_SYS_CSPR7);
- set_ifc_amask(IFC_CS7, CONFIG_SYS_AMASK7);
- set_ifc_csor(IFC_CS7, CONFIG_SYS_CSOR7);
+ set_ifc_cspr(IFC_CS7, CFG_SYS_CSPR7);
+ set_ifc_amask(IFC_CS7, CFG_SYS_AMASK7);
+ set_ifc_csor(IFC_CS7, CFG_SYS_CSOR7);
#endif
}
void init_final_memctl_regs(void)
{
-#ifdef CONFIG_SYS_CSPR0_FINAL
- set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0_FINAL);
+#ifdef CFG_SYS_CSPR0_FINAL
+ set_ifc_cspr(IFC_CS0, CFG_SYS_CSPR0_FINAL);
#endif
-#ifdef CONFIG_SYS_AMASK0_FINAL
- set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0);
+#ifdef CFG_SYS_AMASK0_FINAL
+ set_ifc_amask(IFC_CS0, CFG_SYS_AMASK0);
#endif
-#ifdef CONFIG_SYS_CSPR1_FINAL
- set_ifc_cspr(IFC_CS1, CONFIG_SYS_CSPR1_FINAL);
+#ifdef CFG_SYS_CSPR1_FINAL
+ set_ifc_cspr(IFC_CS1, CFG_SYS_CSPR1_FINAL);
#endif
-#ifdef CONFIG_SYS_AMASK1_FINAL
- set_ifc_amask(IFC_CS1, CONFIG_SYS_AMASK1_FINAL);
+#ifdef CFG_SYS_AMASK1_FINAL
+ set_ifc_amask(IFC_CS1, CFG_SYS_AMASK1_FINAL);
#endif
-#ifdef CONFIG_SYS_CSPR2_FINAL
- set_ifc_cspr(IFC_CS2, CONFIG_SYS_CSPR2_FINAL);
+#ifdef CFG_SYS_CSPR2_FINAL
+ set_ifc_cspr(IFC_CS2, CFG_SYS_CSPR2_FINAL);
#endif
-#ifdef CONFIG_SYS_AMASK2_FINAL
- set_ifc_amask(IFC_CS2, CONFIG_SYS_AMASK2);
+#ifdef CFG_SYS_AMASK2_FINAL
+ set_ifc_amask(IFC_CS2, CFG_SYS_AMASK2);
#endif
-#ifdef CONFIG_SYS_CSPR3_FINAL
- set_ifc_cspr(IFC_CS3, CONFIG_SYS_CSPR3_FINAL);
+#ifdef CFG_SYS_CSPR3_FINAL
+ set_ifc_cspr(IFC_CS3, CFG_SYS_CSPR3_FINAL);
#endif
-#ifdef CONFIG_SYS_AMASK3_FINAL
- set_ifc_amask(IFC_CS3, CONFIG_SYS_AMASK3);
+#ifdef CFG_SYS_AMASK3_FINAL
+ set_ifc_amask(IFC_CS3, CFG_SYS_AMASK3);
#endif
}
#endif
diff --git a/drivers/misc/fsl_portals.c b/drivers/misc/fsl_portals.c
index 9c4b4d7..6b83128 100644
--- a/drivers/misc/fsl_portals.c
+++ b/drivers/misc/fsl_portals.c
@@ -20,25 +20,25 @@
#endif
#include <fsl_qbman.h>
-#define MAX_BPORTALS (CONFIG_SYS_BMAN_CINH_SIZE / CONFIG_SYS_BMAN_SP_CINH_SIZE)
-#define MAX_QPORTALS (CONFIG_SYS_QMAN_CINH_SIZE / CONFIG_SYS_QMAN_SP_CINH_SIZE)
+#define MAX_BPORTALS (CFG_SYS_BMAN_CINH_SIZE / CFG_SYS_BMAN_SP_CINH_SIZE)
+#define MAX_QPORTALS (CFG_SYS_QMAN_CINH_SIZE / CFG_SYS_QMAN_SP_CINH_SIZE)
void setup_qbman_portals(void)
{
- void __iomem *bpaddr = (void *)CONFIG_SYS_BMAN_CINH_BASE +
- CONFIG_SYS_BMAN_SWP_ISDR_REG;
- void __iomem *qpaddr = (void *)CONFIG_SYS_QMAN_CINH_BASE +
- CONFIG_SYS_QMAN_SWP_ISDR_REG;
+ void __iomem *bpaddr = (void *)CFG_SYS_BMAN_CINH_BASE +
+ CFG_SYS_BMAN_SWP_ISDR_REG;
+ void __iomem *qpaddr = (void *)CFG_SYS_QMAN_CINH_BASE +
+ CFG_SYS_QMAN_SWP_ISDR_REG;
struct ccsr_qman *qman = (void *)CFG_SYS_FSL_QMAN_ADDR;
/* Set the Qman initiator BAR to match the LAW (for DQRR stashing) */
#ifdef CONFIG_PHYS_64BIT
- out_be32(&qman->qcsp_bare, (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32));
+ out_be32(&qman->qcsp_bare, (u32)(CFG_SYS_QMAN_MEM_PHYS >> 32));
#endif
- out_be32(&qman->qcsp_bar, (u32)CONFIG_SYS_QMAN_MEM_PHYS);
+ out_be32(&qman->qcsp_bar, (u32)CFG_SYS_QMAN_MEM_PHYS);
#ifdef CONFIG_FSL_CORENET
int i;
- for (i = 0; i < CONFIG_SYS_QMAN_NUM_PORTALS; i++) {
+ for (i = 0; i < CFG_SYS_QMAN_NUM_PORTALS; i++) {
u8 sdest = qp_info[i].sdest;
u16 fliodn = qp_info[i].fliodn;
u16 dliodn = qp_info[i].dliodn;
@@ -53,7 +53,7 @@
#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
int i;
- for (i = 0; i < CONFIG_SYS_QMAN_NUM_PORTALS; i++) {
+ for (i = 0; i < CFG_SYS_QMAN_NUM_PORTALS; i++) {
u8 sdest = qp_info[i].sdest;
u16 ficid = qp_info[i].ficid;
u16 dicid = qp_info[i].dicid;
@@ -68,10 +68,10 @@
#endif
/* Change default state of BMan ISDR portals to all 1s */
- inhibit_portals(bpaddr, CONFIG_SYS_BMAN_NUM_PORTALS, MAX_BPORTALS,
- CONFIG_SYS_BMAN_SP_CINH_SIZE);
- inhibit_portals(qpaddr, CONFIG_SYS_QMAN_NUM_PORTALS, MAX_QPORTALS,
- CONFIG_SYS_QMAN_SP_CINH_SIZE);
+ inhibit_portals(bpaddr, CFG_SYS_BMAN_NUM_PORTALS, MAX_BPORTALS,
+ CFG_SYS_BMAN_SP_CINH_SIZE);
+ inhibit_portals(qpaddr, CFG_SYS_QMAN_NUM_PORTALS, MAX_QPORTALS,
+ CFG_SYS_QMAN_SP_CINH_SIZE);
}
void inhibit_portals(void __iomem *addr, int max_portals,
diff --git a/drivers/misc/fsl_sec_mon.c b/drivers/misc/fsl_sec_mon.c
index 321bd27..3597ee2 100644
--- a/drivers/misc/fsl_sec_mon.c
+++ b/drivers/misc/fsl_sec_mon.c
@@ -10,7 +10,7 @@
static u32 get_sec_mon_state(void)
{
struct ccsr_sec_mon_regs *sec_mon_regs = (void *)
- (CONFIG_SYS_SEC_MON_ADDR);
+ (CFG_SYS_SEC_MON_ADDR);
return sec_mon_in32(&sec_mon_regs->hp_stat) & HPSR_SSM_ST_MASK;
}
@@ -19,7 +19,7 @@
u32 sts;
int timeout = 10;
struct ccsr_sec_mon_regs *sec_mon_regs = (void *)
- (CONFIG_SYS_SEC_MON_ADDR);
+ (CFG_SYS_SEC_MON_ADDR);
sts = get_sec_mon_state();
@@ -120,7 +120,7 @@
u32 sts;
int timeout = 10;
struct ccsr_sec_mon_regs *sec_mon_regs = (void *)
- (CONFIG_SYS_SEC_MON_ADDR);
+ (CFG_SYS_SEC_MON_ADDR);
printf("SEC_MON state transitioning to Soft Fail.\n");
sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SW_FSV);
diff --git a/drivers/mmc/fsl_esdhc_spl.c b/drivers/mmc/fsl_esdhc_spl.c
index aa00d7e..6d7c0cf 100644
--- a/drivers/mmc/fsl_esdhc_spl.c
+++ b/drivers/mmc/fsl_esdhc_spl.c
@@ -9,7 +9,7 @@
#include <mmc.h>
#include <malloc.h>
-#ifndef CONFIG_SYS_MMC_U_BOOT_OFFS
+#ifndef CFG_SYS_MMC_U_BOOT_OFFS
extern uchar mmc_u_boot_offs[];
#endif
@@ -97,7 +97,7 @@
}
#ifdef CONFIG_FSL_CORENET
- offset = CONFIG_SYS_MMC_U_BOOT_OFFS;
+ offset = CFG_SYS_MMC_U_BOOT_OFFS;
#else
sector = 0;
again:
@@ -153,16 +153,16 @@
val = *(tmp_buf + blk_off + ESDHC_BOOT_IMAGE_ADDR + i);
offset = (offset << 8) + val;
}
-#ifndef CONFIG_SYS_MMC_U_BOOT_OFFS
+#ifndef CFG_SYS_MMC_U_BOOT_OFFS
offset += (ulong)&mmc_u_boot_offs - CONFIG_SPL_TEXT_BASE;
#else
- offset += CONFIG_SYS_MMC_U_BOOT_OFFS;
+ offset += CFG_SYS_MMC_U_BOOT_OFFS;
#endif
#endif
/*
* Load U-Boot image from mmc into RAM
*/
- code_len = CONFIG_SYS_MMC_U_BOOT_SIZE;
+ code_len = CFG_SYS_MMC_U_BOOT_SIZE;
blk_start = offset / mmc->read_bl_len;
blk_off = offset % mmc->read_bl_len;
blk_cnt = ALIGN(code_len, mmc->read_bl_len) / mmc->read_bl_len + 1;
@@ -176,7 +176,7 @@
blk_start++;
}
err = mmc->block_dev.block_read(&mmc->block_dev, blk_start, blk_cnt,
- (uchar *)CONFIG_SYS_MMC_U_BOOT_DST +
+ (uchar *)CFG_SYS_MMC_U_BOOT_DST +
(blk_off ? (mmc->read_bl_len - blk_off) : 0));
if (err != blk_cnt) {
puts("spl: mmc read failed!!\n");
@@ -189,18 +189,18 @@
* after SDHC DMA transfer.
*/
if (blk_off)
- memcpy((uchar *)CONFIG_SYS_MMC_U_BOOT_DST,
+ memcpy((uchar *)CFG_SYS_MMC_U_BOOT_DST,
tmp_buf + blk_off, mmc->read_bl_len - blk_off);
/*
* Clean d-cache and invalidate i-cache, to
* make sure that no stale data is executed.
*/
- flush_cache(CONFIG_SYS_MMC_U_BOOT_DST, CONFIG_SYS_MMC_U_BOOT_SIZE);
+ flush_cache(CFG_SYS_MMC_U_BOOT_DST, CFG_SYS_MMC_U_BOOT_SIZE);
/*
* Jump to U-Boot image
*/
- uboot = (void *)CONFIG_SYS_MMC_U_BOOT_START;
+ uboot = (void *)CFG_SYS_MMC_U_BOOT_START;
(*uboot)();
}
diff --git a/drivers/mmc/gen_atmel_mci.c b/drivers/mmc/gen_atmel_mci.c
index 607a223..d91819a 100644
--- a/drivers/mmc/gen_atmel_mci.c
+++ b/drivers/mmc/gen_atmel_mci.c
@@ -24,8 +24,8 @@
#include <asm/arch/hardware.h>
#include "atmel_mci.h"
-#ifndef CONFIG_SYS_MMC_CLK_OD
-# define CONFIG_SYS_MMC_CLK_OD 150000
+#ifndef CFG_SYS_MMC_CLK_OD
+# define CFG_SYS_MMC_CLK_OD 150000
#endif
#define MMC_DEFAULT_BLKLEN 512
@@ -448,9 +448,9 @@
/* Set default clocks and blocklen */
#ifdef CONFIG_DM_MMC
- mci_set_mode(dev, CONFIG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN);
+ mci_set_mode(dev, CFG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN);
#else
- mci_set_mode(mmc, CONFIG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN);
+ mci_set_mode(mmc, CFG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN);
#endif
return 0;
diff --git a/drivers/mmc/sh_sdhi.c b/drivers/mmc/sh_sdhi.c
index b2d0fac..3ce7cbf 100644
--- a/drivers/mmc/sh_sdhi.c
+++ b/drivers/mmc/sh_sdhi.c
@@ -761,7 +761,7 @@
struct mmc *mmc;
struct sh_sdhi_host *host = NULL;
- if (ch >= CONFIG_SYS_SH_SDHI_NR_CHANNEL)
+ if (ch >= CFG_SYS_SH_SDHI_NR_CHANNEL)
return -ENODEV;
host = malloc(sizeof(struct sh_sdhi_host));
diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c
index d34d8ee..c1cdd2c 100644
--- a/drivers/mtd/cfi_flash.c
+++ b/drivers/mtd/cfi_flash.c
@@ -53,7 +53,7 @@
* AMD/Spansion Application Note: Migration from Single-byte to Three-byte
* Device IDs, Publication Number 25538 Revision A, November 8, 2001
*
- * Define CONFIG_SYS_WRITE_SWAPPED_DATA, if you have to swap the Bytes between
+ * Define CFG_SYS_WRITE_SWAPPED_DATA, if you have to swap the Bytes between
* reading and writing ... (yes there is such a Hardware).
*/
@@ -119,14 +119,14 @@
#else
__weak phys_addr_t cfi_flash_bank_addr(int i)
{
- return ((phys_addr_t [])CONFIG_SYS_FLASH_BANKS_LIST)[i];
+ return ((phys_addr_t [])CFG_SYS_FLASH_BANKS_LIST)[i];
}
#endif
__weak unsigned long cfi_flash_bank_size(int i)
{
-#ifdef CONFIG_SYS_FLASH_BANKS_SIZES
- return ((unsigned long [])CONFIG_SYS_FLASH_BANKS_SIZES)[i];
+#ifdef CFG_SYS_FLASH_BANKS_SIZES
+ return ((unsigned long [])CFG_SYS_FLASH_BANKS_SIZES)[i];
#else
return 0;
#endif
@@ -178,7 +178,7 @@
*/
#if defined(CONFIG_ENV_IS_IN_FLASH) || defined(CONFIG_ENV_ADDR_REDUND) || \
(defined(CONFIG_SYS_MONITOR_BASE) && \
- (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE))
+ (CONFIG_SYS_MONITOR_BASE >= CFG_SYS_FLASH_BASE))
static flash_info_t *flash_get_info(ulong base)
{
int i;
@@ -227,7 +227,7 @@
int i;
int cword_offset;
int cp_offset;
-#if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
+#if defined(__LITTLE_ENDIAN) || defined(CFG_SYS_WRITE_SWAPPED_DATA)
u32 cmd_le = cpu_to_le32(cmd);
#endif
uchar val;
@@ -235,7 +235,7 @@
for (i = info->portwidth; i > 0; i--) {
cword_offset = (info->portwidth - i) % info->chipwidth;
-#if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
+#if defined(__LITTLE_ENDIAN) || defined(CFG_SYS_WRITE_SWAPPED_DATA)
cp_offset = info->portwidth - i;
val = *((uchar *)&cmd_le + cword_offset);
#else
@@ -292,7 +292,7 @@
uchar retval;
cp = flash_map(info, 0, offset);
-#if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
+#if defined(__LITTLE_ENDIAN) || defined(CFG_SYS_WRITE_SWAPPED_DATA)
retval = flash_read8(cp);
#else
retval = flash_read8(cp + info->portwidth - 1);
@@ -335,7 +335,7 @@
for (x = 0; x < 4 * info->portwidth; x++)
debug("addr[%x] = 0x%x\n", x, flash_read8(addr + x));
#endif
-#if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
+#if defined(__LITTLE_ENDIAN) || defined(CFG_SYS_WRITE_SWAPPED_DATA)
retval = ((flash_read8(addr) << 16) |
(flash_read8(addr + info->portwidth) << 24) |
(flash_read8(addr + 2 * info->portwidth)) |
@@ -580,7 +580,7 @@
#endif
/* Wait for command completion */
-#ifdef CONFIG_SYS_LOW_RES_TIMER
+#ifdef CFG_SYS_LOW_RES_TIMER
reset_timer();
#endif
start = get_timer(0);
@@ -673,7 +673,7 @@
#endif
/* Wait for command completion */
-#ifdef CONFIG_SYS_LOW_RES_TIMER
+#ifdef CFG_SYS_LOW_RES_TIMER
reset_timer();
#endif
start = get_timer(0);
@@ -713,7 +713,7 @@
*/
static void flash_add_byte(flash_info_t *info, cfiword_t *cword, uchar c)
{
-#if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
+#if defined(__LITTLE_ENDIAN) && !defined(CFG_SYS_WRITE_SWAPPED_DATA)
unsigned short w;
unsigned int l;
unsigned long long ll;
@@ -724,7 +724,7 @@
cword->w8 = c;
break;
case FLASH_CFI_16BIT:
-#if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
+#if defined(__LITTLE_ENDIAN) && !defined(CFG_SYS_WRITE_SWAPPED_DATA)
w = c;
w <<= 8;
cword->w16 = (cword->w16 >> 8) | w;
@@ -733,7 +733,7 @@
#endif
break;
case FLASH_CFI_32BIT:
-#if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
+#if defined(__LITTLE_ENDIAN) && !defined(CFG_SYS_WRITE_SWAPPED_DATA)
l = c;
l <<= 24;
cword->w32 = (cword->w32 >> 8) | l;
@@ -742,7 +742,7 @@
#endif
break;
case FLASH_CFI_64BIT:
-#if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
+#if defined(__LITTLE_ENDIAN) && !defined(CFG_SYS_WRITE_SWAPPED_DATA)
ll = c;
ll <<= 56;
cword->w64 = (cword->w64 >> 8) | ll;
@@ -2359,7 +2359,7 @@
/* Monitor protection ON by default */
#if defined(CONFIG_SYS_MONITOR_BASE) && \
- (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE) && \
+ (CONFIG_SYS_MONITOR_BASE >= CFG_SYS_FLASH_BASE) && \
(!defined(CONFIG_MONITOR_IS_IN_RAM))
flash_protect(FLAG_PROTECT_SET,
CONFIG_SYS_MONITOR_BASE,
diff --git a/drivers/mtd/nand/raw/fsl_ifc_nand.c b/drivers/mtd/nand/raw/fsl_ifc_nand.c
index 59de325..18abd75 100644
--- a/drivers/mtd/nand/raw/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/raw/fsl_ifc_nand.c
@@ -780,10 +780,10 @@
ver = ifc_in32(&ifc_ctrl->regs.gregs->ifc_rev);
if (ver >= FSL_IFC_V2_0_0)
ifc_ctrl->regs.rregs =
- (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_64KOFFSET;
+ (void *)CFG_SYS_IFC_ADDR + IFC_RREGS_64KOFFSET;
else
ifc_ctrl->regs.rregs =
- (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_4KOFFSET;
+ (void *)CFG_SYS_IFC_ADDR + IFC_RREGS_4KOFFSET;
/* clear event registers */
ifc_out32(&ifc_ctrl->regs.rregs->ifc_nand.nand_evter_stat, ~0U);
diff --git a/drivers/mtd/nand/raw/fsl_ifc_spl.c b/drivers/mtd/nand/raw/fsl_ifc_spl.c
index 7d4b77d..3b464ce 100644
--- a/drivers/mtd/nand/raw/fsl_ifc_spl.c
+++ b/drivers/mtd/nand/raw/fsl_ifc_spl.c
@@ -54,14 +54,14 @@
static inline struct fsl_ifc_runtime *runtime_regs_address(void)
{
- struct fsl_ifc regs = {(void *)CONFIG_SYS_IFC_ADDR, NULL};
+ struct fsl_ifc regs = {(void *)CFG_SYS_IFC_ADDR, NULL};
int ver = 0;
ver = ifc_in32(®s.gregs->ifc_rev);
if (ver >= FSL_IFC_V2_0_0)
- regs.rregs = (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_64KOFFSET;
+ regs.rregs = (void *)CFG_SYS_IFC_ADDR + IFC_RREGS_64KOFFSET;
else
- regs.rregs = (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_4KOFFSET;
+ regs.rregs = (void *)CFG_SYS_IFC_ADDR + IFC_RREGS_4KOFFSET;
return regs.rregs;
}
@@ -108,7 +108,7 @@
int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
{
- struct fsl_ifc_fcm *gregs = (void *)CONFIG_SYS_IFC_ADDR;
+ struct fsl_ifc_fcm *gregs = (void *)CFG_SYS_IFC_ADDR;
struct fsl_ifc_runtime *ifc = NULL;
uchar *buf = (uchar *)CFG_SYS_NAND_BASE;
int page_size;
diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c
index 5bc5301..a884c65 100644
--- a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c
+++ b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c
@@ -84,8 +84,8 @@
static struct lpc32xx_nand_mlc_registers __iomem *lpc32xx_nand_mlc_registers
= (struct lpc32xx_nand_mlc_registers __iomem *)MLC_NAND_BASE;
-#if !defined(CONFIG_SYS_MAX_NAND_CHIPS)
-#define CONFIG_SYS_MAX_NAND_CHIPS 1
+#if !defined(CFG_SYS_MAX_NAND_CHIPS)
+#define CFG_SYS_MAX_NAND_CHIPS 1
#endif
#define clkdiv(v, w, o) (((1+(clk/v)) & w) << o)
@@ -586,7 +586,7 @@
lpc32xx_nand_init();
/* identify chip */
- ret = nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_CHIPS, NULL);
+ ret = nand_scan_ident(mtd, CFG_SYS_MAX_NAND_CHIPS, NULL);
if (ret) {
pr_err("nand_scan_ident returned %i", ret);
return;
diff --git a/drivers/mtd/onenand/onenand_spl.c b/drivers/mtd/onenand/onenand_spl.c
index ab6f1a8..2699958 100644
--- a/drivers/mtd/onenand/onenand_spl.c
+++ b/drivers/mtd/onenand/onenand_spl.c
@@ -49,12 +49,12 @@
static inline uint16_t onenand_readw(uint32_t addr)
{
- return readw(CONFIG_SYS_ONENAND_BASE + addr);
+ return readw(CFG_SYS_ONENAND_BASE + addr);
}
static inline void onenand_writew(uint16_t value, uint32_t addr)
{
- writew(value, CONFIG_SYS_ONENAND_BASE + addr);
+ writew(value, CFG_SYS_ONENAND_BASE + addr);
}
static enum onenand_spl_pagesize onenand_spl_get_geometry(void)
@@ -82,7 +82,7 @@
static int onenand_spl_read_page(uint32_t block, uint32_t page, uint32_t *buf,
enum onenand_spl_pagesize pagesize)
{
- const uint32_t addr = CONFIG_SYS_ONENAND_BASE + ONENAND_DATARAM;
+ const uint32_t addr = CFG_SYS_ONENAND_BASE + ONENAND_DATARAM;
uint32_t offset;
onenand_writew(onenand_block_address(block),
diff --git a/drivers/mtd/onenand/onenand_uboot.c b/drivers/mtd/onenand/onenand_uboot.c
index 3a8c7b8..04791df 100644
--- a/drivers/mtd/onenand/onenand_uboot.c
+++ b/drivers/mtd/onenand/onenand_uboot.c
@@ -35,7 +35,7 @@
/* It's used for some board init required */
err = onenand_board_init(&onenand_mtd);
#else
- onenand_chip.base = (void *) CONFIG_SYS_ONENAND_BASE;
+ onenand_chip.base = (void *) CFG_SYS_ONENAND_BASE;
#endif
if (!err && !(onenand_scan(&onenand_mtd, 1))) {
diff --git a/drivers/mtd/spi/fsl_espi_spl.c b/drivers/mtd/spi/fsl_espi_spl.c
index 5c41d75..dfc35d6 100644
--- a/drivers/mtd/spi/fsl_espi_spl.c
+++ b/drivers/mtd/spi/fsl_espi_spl.c
@@ -49,8 +49,8 @@
}
#ifdef CONFIG_FSL_CORENET
- offset = CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS;
- code_len = CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE;
+ offset = CFG_SYS_SPI_FLASH_U_BOOT_OFFS;
+ code_len = CFG_SYS_SPI_FLASH_U_BOOT_SIZE;
#else
/*
* Load U-Boot image from SPI flash into RAM
@@ -66,7 +66,7 @@
flash->page_size, (void *)buf);
offset = *(u32 *)(buf + ESPI_BOOT_IMAGE_ADDR);
/* Skip spl code */
- offset += CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS;
+ offset += CFG_SYS_SPI_FLASH_U_BOOT_OFFS;
/* Get the code size from offset 0x48 */
code_len = *(u32 *)(buf + ESPI_BOOT_IMAGE_SIZE);
/* Skip spl code */
@@ -76,7 +76,7 @@
printf("Loading second stage boot loader ");
while (copy_len <= code_len) {
spi_flash_read(flash, offset + copy_len, 0x2000,
- (void *)(CONFIG_SYS_SPI_FLASH_U_BOOT_DST
+ (void *)(CFG_SYS_SPI_FLASH_U_BOOT_DST
+ copy_len));
copy_len = copy_len + 0x2000;
putc('.');
@@ -85,7 +85,7 @@
/*
* Jump to U-Boot image
*/
- flush_cache(CONFIG_SYS_SPI_FLASH_U_BOOT_DST, code_len);
- uboot = (void *)CONFIG_SYS_SPI_FLASH_U_BOOT_START;
+ flush_cache(CFG_SYS_SPI_FLASH_U_BOOT_DST, code_len);
+ uboot = (void *)CFG_SYS_SPI_FLASH_U_BOOT_START;
(*uboot)();
}
diff --git a/drivers/mtd/stm32_flash.c b/drivers/mtd/stm32_flash.c
index 95afa2d..4523344 100644
--- a/drivers/mtd/stm32_flash.c
+++ b/drivers/mtd/stm32_flash.c
@@ -39,7 +39,7 @@
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
flash_info[i].flash_id = FLASH_STM32;
flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
- flash_info[i].start[0] = CONFIG_SYS_FLASH_BASE + (i << 20);
+ flash_info[i].start[0] = CFG_SYS_FLASH_BASE + (i << 20);
flash_info[i].size = sect_sz_kb[0];
for (j = 1; j < CONFIG_SYS_MAX_FLASH_SECT; j++) {
flash_info[i].start[j] = flash_info[i].start[j - 1]
diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index c23e0c0..c8381cc 100644
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c
@@ -128,7 +128,7 @@
struct dtsec *regs = (struct dtsec *)CFG_SYS_FSL_FM1_DTSEC1_ADDR;
/* Assign a Physical address to the TBI */
- out_be32(®s->tbipa, CONFIG_SYS_TBIPA_VALUE);
+ out_be32(®s->tbipa, CFG_SYS_TBIPA_VALUE);
#endif
if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII ||
diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c
index 1d3b7aa..c476cb3 100644
--- a/drivers/net/fm/fm.c
+++ b/drivers/net/fm/fm.c
@@ -67,9 +67,9 @@
void *base = reg;
muram[fm_idx].base = base;
- muram[fm_idx].size = CONFIG_SYS_FM_MURAM_SIZE;
+ muram[fm_idx].size = CFG_SYS_FM_MURAM_SIZE;
muram[fm_idx].alloc = base + FM_MURAM_RES_SIZE;
- muram[fm_idx].top = base + CONFIG_SYS_FM_MURAM_SIZE;
+ muram[fm_idx].top = base + CFG_SYS_FM_MURAM_SIZE;
}
/*
diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c
index 8443cbb..618c1bc 100644
--- a/drivers/net/fm/init.c
+++ b/drivers/net/fm/init.c
@@ -244,9 +244,9 @@
{
int off;
uint32_t ph;
- phys_addr_t paddr = CONFIG_SYS_CCSRBAR_PHYS + info->compat_offset;
+ phys_addr_t paddr = CFG_SYS_CCSRBAR_PHYS + info->compat_offset;
#ifndef CONFIG_SYS_FMAN_V3
- u64 dtsec1_addr = (u64)CONFIG_SYS_CCSRBAR_PHYS +
+ u64 dtsec1_addr = (u64)CFG_SYS_CCSRBAR_PHYS +
CFG_SYS_FSL_FM1_DTSEC1_OFFSET;
#endif
diff --git a/drivers/net/fsl-mc/dpio/qbman_sys.h b/drivers/net/fsl-mc/dpio/qbman_sys.h
index 8be38e1..ff998d4 100644
--- a/drivers/net/fsl-mc/dpio/qbman_sys.h
+++ b/drivers/net/fsl-mc/dpio/qbman_sys.h
@@ -256,12 +256,12 @@
s->addr_cena = d->cena_bar;
s->addr_cinh = d->cinh_bar;
- s->cena = (void *)valloc(CONFIG_SYS_PAGE_SIZE);
+ s->cena = (void *)valloc(CFG_SYS_PAGE_SIZE);
if (!s->cena) {
printf("Could not allocate page for cena shadow\n");
return -1;
}
- memset((void *)s->cena, 0x00, CONFIG_SYS_PAGE_SIZE);
+ memset((void *)s->cena, 0x00, CFG_SYS_PAGE_SIZE);
#ifdef QBMAN_CHECKING
/* We should never be asked to initialise for a portal that isn't in
diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
index 68833f9..69da465 100644
--- a/drivers/net/fsl-mc/mc.c
+++ b/drivers/net/fsl-mc/mc.c
@@ -54,7 +54,7 @@
static struct mc_version mc_ver_info;
static int mc_boot_status = -1;
static int mc_dpl_applied = -1;
-#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
+#ifdef CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
static int mc_aiop_applied = -1;
#endif
struct fsl_mc_io *root_mc_io = NULL;
@@ -500,13 +500,13 @@
int dpc_size;
#endif
-#ifdef CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET
- BUILD_BUG_ON((CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET & 0x3) != 0 ||
- CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET > 0xffffffff);
+#ifdef CFG_SYS_LS_MC_DRAM_DPC_OFFSET
+ BUILD_BUG_ON((CFG_SYS_LS_MC_DRAM_DPC_OFFSET & 0x3) != 0 ||
+ CFG_SYS_LS_MC_DRAM_DPC_OFFSET > 0xffffffff);
- mc_dpc_offset = CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET;
+ mc_dpc_offset = CFG_SYS_LS_MC_DRAM_DPC_OFFSET;
#else
-#error "CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET not defined"
+#error "CFG_SYS_LS_MC_DRAM_DPC_OFFSET not defined"
#endif
/*
@@ -531,7 +531,7 @@
}
dpc_size = fdt_totalsize(dpc_fdt_hdr);
- if (dpc_size > CONFIG_SYS_LS_MC_DPC_MAX_LENGTH) {
+ if (dpc_size > CFG_SYS_LS_MC_DPC_MAX_LENGTH) {
printf("\nfsl-mc: ERROR: Bad DPC image (too large: %d)\n",
dpc_size);
return -EINVAL;
@@ -576,13 +576,13 @@
int dpl_size;
#endif
-#ifdef CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET
- BUILD_BUG_ON((CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET & 0x3) != 0 ||
- CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET > 0xffffffff);
+#ifdef CFG_SYS_LS_MC_DRAM_DPL_OFFSET
+ BUILD_BUG_ON((CFG_SYS_LS_MC_DRAM_DPL_OFFSET & 0x3) != 0 ||
+ CFG_SYS_LS_MC_DRAM_DPL_OFFSET > 0xffffffff);
- mc_dpl_offset = CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET;
+ mc_dpl_offset = CFG_SYS_LS_MC_DRAM_DPL_OFFSET;
#else
-#error "CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET not defined"
+#error "CFG_SYS_LS_MC_DRAM_DPL_OFFSET not defined"
#endif
/*
@@ -603,7 +603,7 @@
}
dpl_size = fdt_totalsize(dpl_fdt_hdr);
- if (dpl_size > CONFIG_SYS_LS_MC_DPL_MAX_LENGTH) {
+ if (dpl_size > CFG_SYS_LS_MC_DPL_MAX_LENGTH) {
printf("\nfsl-mc: ERROR: Bad DPL image (too large: %d)\n",
dpl_size);
return -EINVAL;
@@ -624,7 +624,7 @@
*/
static unsigned long get_mc_boot_timeout_ms(void)
{
- unsigned long timeout_ms = CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS;
+ unsigned long timeout_ms = CFG_SYS_LS_MC_BOOT_TIMEOUT_MS;
char *timeout_ms_env_var = env_get(MC_BOOT_TIMEOUT_ENV_VAR);
@@ -636,14 +636,14 @@
"\' environment variable: %lu\n",
timeout_ms);
- timeout_ms = CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS;
+ timeout_ms = CFG_SYS_LS_MC_BOOT_TIMEOUT_MS;
}
}
return timeout_ms;
}
-#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
+#ifdef CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
__weak bool soc_has_aiop(void)
{
@@ -666,12 +666,12 @@
#ifdef CONFIG_SYS_LS_MC_DPC_IN_DDR
printf("MC AIOP is preloaded to %#llx\n", mc_ram_addr +
- CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET);
+ CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET);
#else
aiop_img = (void *)aiop_fw_addr;
mc_copy_image("MC AIOP image",
- (u64)aiop_img, CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH,
- mc_ram_addr + CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET);
+ (u64)aiop_img, CFG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH,
+ mc_ram_addr + CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET);
#endif
mc_aiop_applied = 0;
@@ -896,7 +896,7 @@
return mc_boot_status;
}
-#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
+#ifdef CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
int get_aiop_apply_status(void)
{
return mc_aiop_applied;
@@ -938,14 +938,14 @@
*/
unsigned long mc_get_dram_block_size(void)
{
- unsigned long dram_block_size = CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE;
+ unsigned long dram_block_size = CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE;
char *dram_block_size_env_var = env_get(MC_MEM_SIZE_ENV_VAR);
if (dram_block_size_env_var) {
dram_block_size = hextoul(dram_block_size_env_var, NULL);
- if (dram_block_size < CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE) {
+ if (dram_block_size < CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE) {
printf("fsl-mc: WARNING: Invalid value for \'"
MC_MEM_SIZE_ENV_VAR
"\' environment variable: %lu\n",
@@ -1838,7 +1838,7 @@
case 's': {
char sub_cmd;
u64 mc_fw_addr, mc_dpc_addr;
-#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
+#ifdef CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
u64 aiop_fw_addr;
#endif
if (argc < 3)
@@ -1864,7 +1864,7 @@
err = mc_init_object();
break;
-#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
+#ifdef CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
case 'a':
if (argc < 4)
goto usage;
diff --git a/drivers/net/fsl_mcdmafec.c b/drivers/net/fsl_mcdmafec.c
index 6825f9e..cc61a10 100644
--- a/drivers/net/fsl_mcdmafec.c
+++ b/drivers/net/fsl_mcdmafec.c
@@ -43,11 +43,11 @@
static void init_eth_info(struct fec_info_dma *info)
{
/* setup Receive and Transmit buffer descriptor */
-#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
+#ifdef CFG_SYS_FEC_BUF_USE_SRAM
static u32 tmp;
if (info->index == 0)
- tmp = CONFIG_SYS_INIT_RAM_ADDR + 0x1000;
+ tmp = CFG_SYS_INIT_RAM_ADDR + 0x1000;
else
info->rxbd = (cbd_t *)DBUF_LENGTH;
@@ -59,7 +59,7 @@
tmp = (u32)info->txbd;
info->txbuf =
(char *)((u32)info->txbuf + tmp +
- (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
+ (CFG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
tmp = (u32)info->txbuf;
#else
info->rxbd =
@@ -67,7 +67,7 @@
(PKTBUFSRX * sizeof(cbd_t)));
info->txbd =
(cbd_t *)memalign(CONFIG_SYS_CACHELINE_SIZE,
- (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
+ (CFG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
info->txbuf =
(char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH);
#endif
@@ -283,15 +283,15 @@
/* Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
* Settings: Last, Tx CRC */
- for (i = 0; i < CONFIG_SYS_TX_ETH_BUFFER; i++) {
+ for (i = 0; i < CFG_SYS_TX_ETH_BUFFER; i++) {
info->txbd[i].cbd_sc = 0;
info->txbd[i].cbd_datlen = 0;
info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]);
}
- info->txbd[CONFIG_SYS_TX_ETH_BUFFER - 1].cbd_sc |= BD_ENET_TX_WRAP;
+ info->txbd[CFG_SYS_TX_ETH_BUFFER - 1].cbd_sc |= BD_ENET_TX_WRAP;
info->used_tbd_idx = 0;
- info->clean_tbd_num = CONFIG_SYS_TX_ETH_BUFFER;
+ info->clean_tbd_num = CFG_SYS_TX_ETH_BUFFER;
/* Set Rx FIFO alarm and granularity value */
fecp->rfcr = 0x0c000000;
@@ -352,7 +352,7 @@
miiphy_read(dev->name, info->phy_addr, MII_BMSR, &phy_status);
/* process all the consumed TBDs */
- while (info->clean_tbd_num < CONFIG_SYS_TX_ETH_BUFFER) {
+ while (info->clean_tbd_num < CFG_SYS_TX_ETH_BUFFER) {
p_used_tbd = &info->txbd[info->used_tbd_idx];
if (p_used_tbd->cbd_sc & BD_ENET_TX_READY) {
#ifdef ET_DEBUG
@@ -363,7 +363,7 @@
}
/* clean this buffer descriptor */
- if (info->used_tbd_idx == (CONFIG_SYS_TX_ETH_BUFFER - 1))
+ if (info->used_tbd_idx == (CFG_SYS_TX_ETH_BUFFER - 1))
p_used_tbd->cbd_sc = BD_ENET_TX_WRAP;
else
p_used_tbd->cbd_sc = 0;
@@ -371,7 +371,7 @@
/* update some indeces for a correct handling of TBD ring */
info->clean_tbd_num++;
info->used_tbd_idx = (info->used_tbd_idx + 1)
- % CONFIG_SYS_TX_ETH_BUFFER;
+ % CFG_SYS_TX_ETH_BUFFER;
}
/* Check for valid length of data. */
@@ -389,7 +389,7 @@
p_tbd->cbd_datlen = length;
p_tbd->cbd_bufaddr = (u32)packet;
p_tbd->cbd_sc |= BD_ENET_TX_LAST | BD_ENET_TX_TC | BD_ENET_TX_READY;
- info->tx_idx = (info->tx_idx + 1) % CONFIG_SYS_TX_ETH_BUFFER;
+ info->tx_idx = (info->tx_idx + 1) % CFG_SYS_TX_ETH_BUFFER;
/* Enable DMA transmit task */
MCD_continDma(info->tx_task);
@@ -524,8 +524,8 @@
if (val)
info->tx_init = fdt32_to_cpu(*val);
-#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
- u32 tmp = CONFIG_SYS_INIT_RAM_ADDR + 0x1000;
+#ifdef CFG_SYS_FEC_BUF_USE_SRAM
+ u32 tmp = CFG_SYS_INIT_RAM_ADDR + 0x1000;
#endif
init_eth_info(info);
diff --git a/drivers/net/mcffec.c b/drivers/net/mcffec.c
index 4dd8489..ec1fae9 100644
--- a/drivers/net/mcffec.c
+++ b/drivers/net/mcffec.c
@@ -39,11 +39,11 @@
static void init_eth_info(struct fec_info_s *info)
{
-#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
+#ifdef CFG_SYS_FEC_BUF_USE_SRAM
static u32 tmp;
if (info->index == 0)
- tmp = CONFIG_SYS_INIT_RAM_ADDR + 0x1000;
+ tmp = CFG_SYS_INIT_RAM_ADDR + 0x1000;
else
info->rxbd = (cbd_t *)DBUF_LENGTH;
@@ -56,7 +56,7 @@
tmp = (u32)info->txbd;
info->txbuf =
(char *)((u32)info->txbuf + tmp +
- (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
+ (CFG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
tmp = (u32)info->txbuf;
#else
info->rxbd =
@@ -387,7 +387,7 @@
/* Activate transmit Buffer Descriptor polling */
fecp->tdar = 0x01000000; /* Descriptor polling active */
-#ifndef CONFIG_SYS_FEC_BUF_USE_SRAM
+#ifndef CFG_SYS_FEC_BUF_USE_SRAM
/*
* FEC unable to initial transmit data packet.
* A nop will ensure the descriptor polling active completed.
diff --git a/drivers/net/qe/uec.h b/drivers/net/qe/uec.h
index 32b7d3e..551d706 100644
--- a/drivers/net/qe/uec.h
+++ b/drivers/net/qe/uec.h
@@ -605,10 +605,10 @@
#define STD_UEC_INFO(num) \
{ \
.uf_info = { \
- .ucc_num = CONFIG_SYS_UEC##num##_UCC_NUM,\
- .rx_clock = CONFIG_SYS_UEC##num##_RX_CLK, \
- .tx_clock = CONFIG_SYS_UEC##num##_TX_CLK, \
- .eth_type = CONFIG_SYS_UEC##num##_ETH_TYPE,\
+ .ucc_num = CFG_SYS_UEC##num##_UCC_NUM,\
+ .rx_clock = CFG_SYS_UEC##num##_RX_CLK, \
+ .tx_clock = CFG_SYS_UEC##num##_TX_CLK, \
+ .eth_type = CFG_SYS_UEC##num##_ETH_TYPE,\
}, \
.num_threads_tx = UEC_NUM_OF_THREADS_1, \
.num_threads_rx = UEC_NUM_OF_THREADS_1, \
@@ -616,9 +616,9 @@
.risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, \
.tx_bd_ring_len = 16, \
.rx_bd_ring_len = 16, \
- .phy_address = CONFIG_SYS_UEC##num##_PHY_ADDR, \
- .enet_interface_type = CONFIG_SYS_UEC##num##_INTERFACE_TYPE, \
- .speed = CONFIG_SYS_UEC##num##_INTERFACE_SPEED, \
+ .phy_address = CFG_SYS_UEC##num##_PHY_ADDR, \
+ .enet_interface_type = CFG_SYS_UEC##num##_INTERFACE_TYPE, \
+ .speed = CFG_SYS_UEC##num##_INTERFACE_SPEED, \
}
struct uec_inf {
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index d69a9ff..8b6f034 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -764,7 +764,7 @@
priv->phyregs_sgmii = tsec_info->miiregs_sgmii;
priv->phyaddr = tsec_info->phyaddr;
- priv->tbiaddr = CONFIG_SYS_TBIPA_VALUE;
+ priv->tbiaddr = CFG_SYS_TBIPA_VALUE;
priv->flags = tsec_info->flags;
strcpy(dev->name, tsec_info->devname);
@@ -832,7 +832,7 @@
struct eth_pdata *pdata = dev_get_plat(dev);
struct tsec_private *priv = dev_get_priv(dev);
struct ofnode_phandle_args phandle_args;
- u32 tbiaddr = CONFIG_SYS_TBIPA_VALUE;
+ u32 tbiaddr = CFG_SYS_TBIPA_VALUE;
struct tsec_data *data;
ofnode parent, child;
fdt_addr_t reg;
diff --git a/drivers/net/vsc7385.c b/drivers/net/vsc7385.c
index af8d99c..09883f0 100644
--- a/drivers/net/vsc7385.c
+++ b/drivers/net/vsc7385.c
@@ -39,13 +39,13 @@
u8 *fw = firmware;
unsigned int i;
- u32 *gloreset = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c050);
- u32 *icpu_ctrl = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c040);
- u32 *icpu_addr = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c044);
- u32 *icpu_data = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c048);
- u32 *icpu_rom_map = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c070);
+ u32 *gloreset = (u32 *) (CFG_SYS_VSC7385_BASE + 0x1c050);
+ u32 *icpu_ctrl = (u32 *) (CFG_SYS_VSC7385_BASE + 0x1c040);
+ u32 *icpu_addr = (u32 *) (CFG_SYS_VSC7385_BASE + 0x1c044);
+ u32 *icpu_data = (u32 *) (CFG_SYS_VSC7385_BASE + 0x1c048);
+ u32 *icpu_rom_map = (u32 *) (CFG_SYS_VSC7385_BASE + 0x1c070);
#ifdef DEBUG
- u32 *chipid = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c060);
+ u32 *chipid = (u32 *) (CFG_SYS_VSC7385_BASE + 0x1c060);
#endif
out_be32(gloreset, 3);
diff --git a/drivers/power/power_dialog.c b/drivers/power/power_dialog.c
index e286dd1..ad7aaf3 100644
--- a/drivers/power/power_dialog.c
+++ b/drivers/power/power_dialog.c
@@ -24,7 +24,7 @@
p->number_of_regs = DIALOG_NUM_OF_REGS;
p->interface = PMIC_I2C;
- p->hw.i2c.addr = CONFIG_SYS_DIALOG_PMIC_I2C_ADDR;
+ p->hw.i2c.addr = CFG_SYS_DIALOG_PMIC_I2C_ADDR;
p->hw.i2c.tx_num = 1;
p->bus = bus;
diff --git a/drivers/qe/uec.h b/drivers/qe/uec.h
index 83461c0..63371e7 100644
--- a/drivers/qe/uec.h
+++ b/drivers/qe/uec.h
@@ -605,10 +605,10 @@
#define STD_UEC_INFO(num) \
{ \
.uf_info = { \
- .ucc_num = CONFIG_SYS_UEC##num##_UCC_NUM,\
- .rx_clock = CONFIG_SYS_UEC##num##_RX_CLK, \
- .tx_clock = CONFIG_SYS_UEC##num##_TX_CLK, \
- .eth_type = CONFIG_SYS_UEC##num##_ETH_TYPE,\
+ .ucc_num = CFG_SYS_UEC##num##_UCC_NUM,\
+ .rx_clock = CFG_SYS_UEC##num##_RX_CLK, \
+ .tx_clock = CFG_SYS_UEC##num##_TX_CLK, \
+ .eth_type = CFG_SYS_UEC##num##_ETH_TYPE,\
}, \
.num_threads_tx = UEC_NUM_OF_THREADS_1, \
.num_threads_rx = UEC_NUM_OF_THREADS_1, \
@@ -616,9 +616,9 @@
.risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, \
.tx_bd_ring_len = 16, \
.rx_bd_ring_len = 16, \
- .phy_address = CONFIG_SYS_UEC##num##_PHY_ADDR, \
- .enet_interface_type = CONFIG_SYS_UEC##num##_INTERFACE_TYPE, \
- .speed = CONFIG_SYS_UEC##num##_INTERFACE_SPEED, \
+ .phy_address = CFG_SYS_UEC##num##_PHY_ADDR, \
+ .enet_interface_type = CFG_SYS_UEC##num##_INTERFACE_TYPE, \
+ .speed = CFG_SYS_UEC##num##_INTERFACE_SPEED, \
}
struct uec_inf {
diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c
index 9d429c8..fcf06d1 100644
--- a/drivers/qe/uec_phy.c
+++ b/drivers/qe/uec_phy.c
@@ -52,7 +52,7 @@
*
* Some boards do not have a PHY for each ethernet port. These ports are known
* as Fixed PHY (or PHY-less) ports. For such ports, set the appropriate
- * CONFIG_SYS_UECx_PHY_ADDR equal to CONFIG_FIXED_PHY_ADDR (an unused address)
+ * CFG_SYS_UECx_PHY_ADDR equal to CONFIG_FIXED_PHY_ADDR (an unused address)
* When the drver tries to identify the PHYs, CONFIG_FIXED_PHY will be returned
* and the driver will search CONFIG_SYS_FIXED_PHY_PORTS to find what network
* speed and duplex should be for the port.
@@ -61,10 +61,10 @@
* #define CONFIG_FIXED_PHY 0xFFFFFFFF
* #define CONFIG_SYS_FIXED_PHY_ADDR 0x1E (pick an unused phy address)
*
- * #define CONFIG_SYS_UEC1_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR
- * #define CONFIG_SYS_UEC2_PHY_ADDR 0x02
- * #define CONFIG_SYS_UEC3_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR
- * #define CONFIG_SYS_UEC4_PHY_ADDR 0x04
+ * #define CFG_SYS_UEC1_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR
+ * #define CFG_SYS_UEC2_PHY_ADDR 0x02
+ * #define CFG_SYS_UEC3_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR
+ * #define CFG_SYS_UEC4_PHY_ADDR 0x04
*
* #define CONFIG_SYS_FIXED_PHY_PORT(name,speed,duplex) \
* {name, speed, duplex},
diff --git a/drivers/rtc/ds1307.c b/drivers/rtc/ds1307.c
index 40ca66b..0e9d3d2 100644
--- a/drivers/rtc/ds1307.c
+++ b/drivers/rtc/ds1307.c
@@ -80,8 +80,8 @@
#endif
/*---------------------------------------------------------------------*/
-#ifndef CONFIG_SYS_I2C_RTC_ADDR
-# define CONFIG_SYS_I2C_RTC_ADDR 0x68
+#ifndef CFG_SYS_I2C_RTC_ADDR
+# define CFG_SYS_I2C_RTC_ADDR 0x68
#endif
#if defined(CONFIG_RTC_DS1307) && (CONFIG_SYS_I2C_SPEED > 100000)
@@ -212,13 +212,13 @@
static
uchar rtc_read (uchar reg)
{
- return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg));
+ return (i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg));
}
static void rtc_write (uchar reg, uchar val)
{
- i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
+ i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val);
}
#endif /* !CONFIG_DM_RTC */
diff --git a/drivers/rtc/ds1337.c b/drivers/rtc/ds1337.c
index 486c01f..2c780ab 100644
--- a/drivers/rtc/ds1337.c
+++ b/drivers/rtc/ds1337.c
@@ -184,13 +184,13 @@
static
uchar rtc_read (uchar reg)
{
- return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg));
+ return (i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg));
}
static void rtc_write (uchar reg, uchar val)
{
- i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
+ i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val);
}
#else
static uchar rtc_read(struct udevice *dev, uchar reg)
diff --git a/drivers/rtc/ds1374.c b/drivers/rtc/ds1374.c
index 9f2647d..89442f9 100644
--- a/drivers/rtc/ds1374.c
+++ b/drivers/rtc/ds1374.c
@@ -29,8 +29,8 @@
#endif
/*---------------------------------------------------------------------*/
-#ifndef CONFIG_SYS_I2C_RTC_ADDR
-# define CONFIG_SYS_I2C_RTC_ADDR 0x68
+#ifndef CFG_SYS_I2C_RTC_ADDR
+# define CFG_SYS_I2C_RTC_ADDR 0x68
#endif
#if defined(CONFIG_RTC_DS1374) && (CONFIG_SYS_I2C_SPEED > 400000)
@@ -194,21 +194,21 @@
*/
static uchar rtc_read (uchar reg)
{
- return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg));
+ return (i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg));
}
static void rtc_write(uchar reg, uchar val, bool set)
{
if (set == true) {
- val |= i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg);
- i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
+ val |= i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg);
+ i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val);
} else {
- val = i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg) & ~val;
- i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
+ val = i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg) & ~val;
+ i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val);
}
}
static void rtc_write_raw (uchar reg, uchar val)
{
- i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
+ i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val);
}
diff --git a/drivers/rtc/ds3231.c b/drivers/rtc/ds3231.c
index 5b72e86..bd32ed2 100644
--- a/drivers/rtc/ds3231.c
+++ b/drivers/rtc/ds3231.c
@@ -164,13 +164,13 @@
static
uchar rtc_read (uchar reg)
{
- return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg));
+ return (i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg));
}
static void rtc_write (uchar reg, uchar val)
{
- i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
+ i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val);
}
#else
static int ds3231_rtc_get(struct udevice *dev, struct rtc_time *tmp)
diff --git a/drivers/rtc/m41t62.c b/drivers/rtc/m41t62.c
index 8be532c..66a0faa 100644
--- a/drivers/rtc/m41t62.c
+++ b/drivers/rtc/m41t62.c
@@ -319,7 +319,7 @@
{
u8 buf[M41T62_DATETIME_REG_SIZE];
- i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE);
+ i2c_read(CFG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE);
m41t62_update_rtc_time(tm, buf);
return 0;
@@ -329,10 +329,10 @@
{
u8 buf[M41T62_DATETIME_REG_SIZE];
- i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE);
+ i2c_read(CFG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE);
m41t62_set_rtc_buf(tm, buf);
- if (i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf,
+ if (i2c_write(CFG_SYS_I2C_RTC_ADDR, 0, 1, buf,
M41T62_DATETIME_REG_SIZE)) {
printf("I2C write failed in %s()\n", __func__);
return -1;
@@ -349,8 +349,8 @@
* M41T82: Make sure HT (Halt Update) bit is cleared.
* This bit is 0 in M41T62 so its save to clear it always.
*/
- i2c_read(CONFIG_SYS_I2C_RTC_ADDR, M41T62_REG_ALARM_HOUR, 1, &val, 1);
+ i2c_read(CFG_SYS_I2C_RTC_ADDR, M41T62_REG_ALARM_HOUR, 1, &val, 1);
val &= ~M41T80_ALHOUR_HT;
- i2c_write(CONFIG_SYS_I2C_RTC_ADDR, M41T62_REG_ALARM_HOUR, 1, &val, 1);
+ i2c_write(CFG_SYS_I2C_RTC_ADDR, M41T62_REG_ALARM_HOUR, 1, &val, 1);
}
#endif /* CONFIG_DM_RTC */
diff --git a/drivers/rtc/max6900.c b/drivers/rtc/max6900.c
index 1192883..e03a87f 100644
--- a/drivers/rtc/max6900.c
+++ b/drivers/rtc/max6900.c
@@ -16,20 +16,20 @@
#include <i2c.h>
#include <linux/delay.h>
-#ifndef CONFIG_SYS_I2C_RTC_ADDR
-#define CONFIG_SYS_I2C_RTC_ADDR 0x50
+#ifndef CFG_SYS_I2C_RTC_ADDR
+#define CFG_SYS_I2C_RTC_ADDR 0x50
#endif
/* ------------------------------------------------------------------------- */
static uchar rtc_read (uchar reg)
{
- return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg));
+ return (i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg));
}
static void rtc_write (uchar reg, uchar val)
{
- i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
+ i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val);
udelay(2500);
}
diff --git a/drivers/rtc/pcf8563.c b/drivers/rtc/pcf8563.c
index 19faefb..91a4124 100644
--- a/drivers/rtc/pcf8563.c
+++ b/drivers/rtc/pcf8563.c
@@ -111,12 +111,12 @@
static uchar rtc_read (uchar reg)
{
- return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg));
+ return (i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg));
}
static void rtc_write (uchar reg, uchar val)
{
- i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
+ i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val);
}
#else
static int pcf8563_rtc_get(struct udevice *dev, struct rtc_time *tmp)
diff --git a/drivers/rtc/pt7c4338.c b/drivers/rtc/pt7c4338.c
index c987494..e0a7bd3 100644
--- a/drivers/rtc/pt7c4338.c
+++ b/drivers/rtc/pt7c4338.c
@@ -53,12 +53,12 @@
/****** Helper functions ****************************************/
static u8 rtc_read(u8 reg)
{
- return i2c_reg_read(CONFIG_SYS_I2C_RTC_ADDR, reg);
+ return i2c_reg_read(CFG_SYS_I2C_RTC_ADDR, reg);
}
static void rtc_write(u8 reg, u8 val)
{
- i2c_reg_write(CONFIG_SYS_I2C_RTC_ADDR, reg, val);
+ i2c_reg_write(CFG_SYS_I2C_RTC_ADDR, reg, val);
}
/****************************************************************/
diff --git a/drivers/rtc/rs5c372.c b/drivers/rtc/rs5c372.c
index 97ec001..6b1c23c 100644
--- a/drivers/rtc/rs5c372.c
+++ b/drivers/rtc/rs5c372.c
@@ -39,8 +39,8 @@
#define rtc_debug 0 /* gcc will remove all the debug code for us */
#endif
-#ifndef CONFIG_SYS_I2C_RTC_ADDR
-#define CONFIG_SYS_I2C_RTC_ADDR 0x32
+#ifndef CFG_SYS_I2C_RTC_ADDR
+#define CFG_SYS_I2C_RTC_ADDR 0x32
#endif
#define RS5C372_RAM_SIZE 0x10
@@ -63,7 +63,7 @@
{
int ret;
- ret = i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, len);
+ ret = i2c_read(CFG_SYS_I2C_RTC_ADDR, 0, 0, buf, len);
if (ret != 0) {
printf("%s: failed to read\n", __FUNCTION__);
return ret;
@@ -103,7 +103,7 @@
buf[14] = 0; /* reg. 13 */
buf[15] = 0; /* reg. 14 */
buf[16] = USE_24HOUR_MODE; /* reg. 15 */
- ret = i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, RS5C372_RAM_SIZE+1);
+ ret = i2c_write(CFG_SYS_I2C_RTC_ADDR, 0, 0, buf, RS5C372_RAM_SIZE+1);
if (ret != 0) {
printf("%s: failed\n", __FUNCTION__);
return;
@@ -204,7 +204,7 @@
memset(buf, 0, sizeof(buf));
/* only read register 15 */
- ret = i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, 1);
+ ret = i2c_read(CFG_SYS_I2C_RTC_ADDR, 0, 0, buf, 1);
if (ret == 0) {
/* need to save register 15 */
@@ -233,7 +233,7 @@
printf("WARNING: year should be between 1970 and 2069!\n");
buf[7] = bin2bcd(tmp->tm_year % 100);
- ret = i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, 8);
+ ret = i2c_write(CFG_SYS_I2C_RTC_ADDR, 0, 0, buf, 8);
if (ret != 0) {
printf("rs5c372_set_datetime(), i2c_master_send() returned %d\n",ret);
return -1;
diff --git a/drivers/rtc/rx8010sj.c b/drivers/rtc/rx8010sj.c
index d513561..bf93b55 100644
--- a/drivers/rtc/rx8010sj.c
+++ b/drivers/rtc/rx8010sj.c
@@ -33,8 +33,8 @@
#endif
/*---------------------------------------------------------------------*/
-#ifndef CONFIG_SYS_I2C_RTC_ADDR
-# define CONFIG_SYS_I2C_RTC_ADDR 0x32
+#ifndef CFG_SYS_I2C_RTC_ADDR
+# define CFG_SYS_I2C_RTC_ADDR 0x32
#endif
/*
@@ -313,7 +313,7 @@
int rtc_get(struct rtc_time *tm)
{
struct ludevice dev = {
- .chip = CONFIG_SYS_I2C_RTC_ADDR,
+ .chip = CFG_SYS_I2C_RTC_ADDR,
};
return rx8010sj_rtc_get(&dev, tm);
@@ -322,7 +322,7 @@
int rtc_set(struct rtc_time *tm)
{
struct ludevice dev = {
- .chip = CONFIG_SYS_I2C_RTC_ADDR,
+ .chip = CFG_SYS_I2C_RTC_ADDR,
};
return rx8010sj_rtc_set(&dev, tm);
@@ -331,7 +331,7 @@
void rtc_reset(void)
{
struct ludevice dev = {
- .chip = CONFIG_SYS_I2C_RTC_ADDR,
+ .chip = CFG_SYS_I2C_RTC_ADDR,
};
rx8010sj_rtc_reset(&dev);
@@ -340,7 +340,7 @@
void rtc_init(void)
{
struct ludevice dev = {
- .chip = CONFIG_SYS_I2C_RTC_ADDR,
+ .chip = CFG_SYS_I2C_RTC_ADDR,
};
rx8010sj_rtc_init(&dev);
diff --git a/drivers/rtc/x1205.c b/drivers/rtc/x1205.c
index ce23427..4a8d1c5 100644
--- a/drivers/rtc/x1205.c
+++ b/drivers/rtc/x1205.c
@@ -77,7 +77,7 @@
static void rtc_write(int reg, u8 val)
{
- i2c_write(CONFIG_SYS_I2C_RTC_ADDR, reg, 2, &val, 1);
+ i2c_write(CFG_SYS_I2C_RTC_ADDR, reg, 2, &val, 1);
}
/*
@@ -89,7 +89,7 @@
{
u8 buf[8];
- i2c_read(CONFIG_SYS_I2C_RTC_ADDR, X1205_CCR_BASE, 2, buf, 8);
+ i2c_read(CFG_SYS_I2C_RTC_ADDR, X1205_CCR_BASE, 2, buf, 8);
debug("%s: raw read data - sec=%02x, min=%02x, hr=%02x, "
"mday=%02x, mon=%02x, year=%02x, wday=%02x, y2k=%02x\n",
diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c
index 83cda1f..8a489a2 100644
--- a/drivers/serial/serial-uclass.c
+++ b/drivers/serial/serial-uclass.c
@@ -25,7 +25,7 @@
/*
* Table with supported baudrates (defined in config_xyz.h)
*/
-static const unsigned long baudrate_table[] = CONFIG_SYS_BAUDRATE_TABLE;
+static const unsigned long baudrate_table[] = CFG_SYS_BAUDRATE_TABLE;
#if CONFIG_IS_ENABLED(SERIAL_PRESENT)
static int serial_check_stdout(const void *blob, struct udevice **devp)
diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c
index 6cdbb89..4d54965 100644
--- a/drivers/serial/serial.c
+++ b/drivers/serial/serial.c
@@ -22,7 +22,7 @@
/*
* Table with supported baudrates (defined in config_xyz.h)
*/
-static const unsigned long baudrate_table[] = CONFIG_SYS_BAUDRATE_TABLE;
+static const unsigned long baudrate_table[] = CFG_SYS_BAUDRATE_TABLE;
/**
* serial_null() - Void registration routine of a serial driver
@@ -459,7 +459,7 @@
}
#if CONFIG_POST & CONFIG_SYS_POST_UART
-static const int bauds[] = CONFIG_SYS_BAUDRATE_TABLE;
+static const int bauds[] = CFG_SYS_BAUDRATE_TABLE;
/**
* uart_post_test() - Test the currently selected serial port using POST
diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c
index 0ee6171..9ebc4ed 100644
--- a/drivers/spi/davinci_spi.c
+++ b/drivers/spi/davinci_spi.c
@@ -225,7 +225,7 @@
SPIPC0_DOFUN_MASK | SPIPC0_DIFUN_MASK), &ds->regs->pc0);
/* setup format */
- scalar = ((CONFIG_SYS_SPI_CLK / ds->freq) - 1) & 0xFF;
+ scalar = ((CFG_SYS_SPI_CLK / ds->freq) - 1) & 0xFF;
/*
* Use following format:
@@ -314,7 +314,7 @@
struct davinci_spi_slave *ds = dev_get_priv(bus);
debug("%s speed %u\n", __func__, max_hz);
- if (max_hz > CONFIG_SYS_SPI_CLK / 2)
+ if (max_hz > CFG_SYS_SPI_CLK / 2)
return -EINVAL;
ds->freq = max_hz;
diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c
index bc5da0a..2bb7390 100644
--- a/drivers/spi/kirkwood_spi.c
+++ b/drivers/spi/kirkwood_spi.c
@@ -131,7 +131,7 @@
* follows:
* SPI actual frequency = core_clk / (SPR * (2 ^ SPPR))
*/
- divider = DIV_ROUND_UP(CONFIG_SYS_TCLK, hz);
+ divider = DIV_ROUND_UP(CFG_SYS_TCLK, hz);
if (divider < 16) {
/* This is the easy case, divider is less than 16 */
spr = divider;
@@ -205,7 +205,7 @@
data = readl(®->timing1);
data &= ~KW_SPI_TMISO_SAMPLE_MASK;
- if (CONFIG_SYS_TCLK == 250000000 &&
+ if (CFG_SYS_TCLK == 250000000 &&
mode & SPI_CPOL &&
mode & SPI_CPHA)
data |= KW_SPI_TMISO_SAMPLE_2;
diff --git a/drivers/sysreset/sysreset_xtfpga.c b/drivers/sysreset/sysreset_xtfpga.c
index ad1781e..84fbc79 100644
--- a/drivers/sysreset/sysreset_xtfpga.c
+++ b/drivers/sysreset/sysreset_xtfpga.c
@@ -15,8 +15,8 @@
{
switch (type) {
case SYSRESET_COLD:
- writel(CONFIG_SYS_FPGAREG_RESET_CODE,
- CONFIG_SYS_FPGAREG_RESET);
+ writel(CFG_SYS_FPGAREG_RESET_CODE,
+ CFG_SYS_FPGAREG_RESET);
break;
default:
return -EPROTONOSUPPORT;
diff --git a/drivers/timer/arm_global_timer.c b/drivers/timer/arm_global_timer.c
index 065f10b..2e50d9f 100644
--- a/drivers/timer/arm_global_timer.c
+++ b/drivers/timer/arm_global_timer.c
@@ -59,7 +59,7 @@
return ret;
uc_priv->clock_rate = ret;
} else {
- uc_priv->clock_rate = CONFIG_SYS_HZ_CLOCK;
+ uc_priv->clock_rate = CFG_SYS_HZ_CLOCK;
}
/* init timer */
diff --git a/drivers/timer/imx-gpt-timer.c b/drivers/timer/imx-gpt-timer.c
index 72be297..9c3b64a 100644
--- a/drivers/timer/imx-gpt-timer.c
+++ b/drivers/timer/imx-gpt-timer.c
@@ -28,9 +28,9 @@
#define GPT_CLKSRC_IPG_CLK (1 << 6)
#define GPT_CLKSRC_IPG_CLK_24M (5 << 6)
-/* If CONFIG_SYS_HZ_CLOCK not specified et's default to 3Mhz */
-#ifndef CONFIG_SYS_HZ_CLOCK
-#define CONFIG_SYS_HZ_CLOCK 3000000
+/* If CFG_SYS_HZ_CLOCK not specified et's default to 3Mhz */
+#ifndef CFG_SYS_HZ_CLOCK
+#define CFG_SYS_HZ_CLOCK 3000000
#endif
struct imx_gpt_timer_regs {
@@ -60,7 +60,7 @@
static int imx_gpt_setup(struct imx_gpt_timer_regs *regs, u32 rate)
{
- u32 prescaler = (rate / CONFIG_SYS_HZ_CLOCK) - 1;
+ u32 prescaler = (rate / CFG_SYS_HZ_CLOCK) - 1;
/* Reset the timer */
setbits_le32(®s->cr, GPT_CR_SWR);
@@ -138,7 +138,7 @@
return ret;
}
- uc_priv->clock_rate = CONFIG_SYS_HZ_CLOCK;
+ uc_priv->clock_rate = CFG_SYS_HZ_CLOCK;
return 0;
}
diff --git a/drivers/timer/orion-timer.c b/drivers/timer/orion-timer.c
index d0eab3c..d588f0c 100644
--- a/drivers/timer/orion-timer.c
+++ b/drivers/timer/orion-timer.c
@@ -72,7 +72,7 @@
if (IS_ENABLED(CONFIG_ARCH_MVEBU))
return MVEBU_TIMER_FIXED_RATE_25MHZ;
else
- return CONFIG_SYS_TCLK;
+ return CFG_SYS_TCLK;
}
/**
@@ -117,7 +117,7 @@
if (type == INPUT_CLOCK_25MHZ)
uc_priv->clock_rate = MVEBU_TIMER_FIXED_RATE_25MHZ;
else
- uc_priv->clock_rate = CONFIG_SYS_TCLK;
+ uc_priv->clock_rate = CFG_SYS_TCLK;
orion_timer_init(priv->base, type);
return 0;
diff --git a/drivers/timer/stm32_timer.c b/drivers/timer/stm32_timer.c
index f07251e..1213a14 100644
--- a/drivers/timer/stm32_timer.c
+++ b/drivers/timer/stm32_timer.c
@@ -97,11 +97,11 @@
rate = clk_get_rate(&clk);
/* we set timer prescaler to obtain a 1MHz timer counter frequency */
- psc = (rate / CONFIG_SYS_HZ_CLOCK) - 1;
+ psc = (rate / CFG_SYS_HZ_CLOCK) - 1;
writel(psc, ®s->psc);
/* Set timer frequency to 1MHz */
- uc_priv->clock_rate = CONFIG_SYS_HZ_CLOCK;
+ uc_priv->clock_rate = CFG_SYS_HZ_CLOCK;
/* Configure timer for auto-reload */
setbits_le32(®s->cr1, CR1_ARPE);
diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
index 9acef5e..3f44181 100644
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -1993,7 +1993,7 @@
gohci.disabled = 1;
gohci.sleeping = 0;
gohci.irq = -1;
- gohci.regs = (struct ohci_regs *)CONFIG_SYS_USB_OHCI_REGS_BASE;
+ gohci.regs = (struct ohci_regs *)CFG_SYS_USB_OHCI_REGS_BASE;
gohci.flags = 0;
gohci.slot_name = CONFIG_SYS_USB_OHCI_SLOT_NAME;
diff --git a/drivers/video/imx/ipu_common.c b/drivers/video/imx/ipu_common.c
index 54d1efc..b0a99c9 100644
--- a/drivers/video/imx/ipu_common.c
+++ b/drivers/video/imx/ipu_common.c
@@ -221,13 +221,13 @@
.usecount = 0,
};
-#if !defined CONFIG_SYS_LDB_CLOCK
-#define CONFIG_SYS_LDB_CLOCK 65000000
+#if !defined CFG_SYS_LDB_CLOCK
+#define CFG_SYS_LDB_CLOCK 65000000
#endif
static struct clk ldb_clk = {
.name = "ldb_clk",
- .rate = CONFIG_SYS_LDB_CLOCK,
+ .rate = CFG_SYS_LDB_CLOCK,
.usecount = 0,
};