global: Move remaining CONFIG_SYS_* to CFG_SYS_*
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do
not easily transition to Kconfig. In many cases they likely should come
from the device tree instead. Move these out of CONFIG namespace and in
to CFG namespace.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index 21491b9..a8af0a1 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -16,10 +16,10 @@
#include <asm/config_mpc85xx.h>
#ifdef CONFIG_SDCARD
-#define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10)
-#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
-#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
-#define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10)
+#define CFG_SYS_MMC_U_BOOT_SIZE (512 << 10)
+#define CFG_SYS_MMC_U_BOOT_DST (0x11000000)
+#define CFG_SYS_MMC_U_BOOT_START (0x11000000)
+#define CFG_SYS_MMC_U_BOOT_OFFS (96 << 10)
#endif
#ifdef CONFIG_SPIFLASH
@@ -27,10 +27,10 @@
#define CONFIG_RAMBOOT_SPIFLASH
#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
#else
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10)
+#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10)
+#define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
+#define CFG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
+#define CFG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10)
#endif
#endif
@@ -111,11 +111,11 @@
extern unsigned long get_sdram_size(void);
#endif
#define CFG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_CCSRBAR 0xffe00000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
+#define CFG_SYS_CCSRBAR 0xffe00000
+#define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR
/*
* Memory map
@@ -136,15 +136,15 @@
*/
/* NOR Flash on IFC */
-#define CONFIG_SYS_FLASH_BASE 0xee000000
+#define CFG_SYS_FLASH_BASE 0xee000000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE)
#else
-#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
+#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE
#endif
-#define CFG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+#define CFG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
@@ -161,7 +161,7 @@
FTIM2_NOR_TWP(0x1c)
#define CFG_SYS_NOR_FTIM3 0x0
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
+#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS}
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
/* CFI for NOR Flash */
@@ -237,85 +237,85 @@
/* Set up IFC registers for boot location NOR/NAND */
#if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT)
-#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR1 CFG_SYS_NOR_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR1 CFG_SYS_NOR_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
#else
-#define CONFIG_SYS_CSPR0 CFG_SYS_NOR_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR0 CFG_SYS_NOR_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
#endif
/* CPLD on IFC */
-#define CONFIG_SYS_CPLD_BASE 0xffb00000
+#define CFG_SYS_CPLD_BASE 0xffb00000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull
+#define CFG_SYS_CPLD_BASE_PHYS 0xfffb00000ull
#else
-#define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
+#define CFG_SYS_CPLD_BASE_PHYS CFG_SYS_CPLD_BASE
#endif
-#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
+#define CFG_SYS_CSPR3 (CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE_PHYS) \
| CSPR_PORT_SIZE_8 \
| CSPR_MSEL_GPCM \
| CSPR_V)
-#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
-#define CONFIG_SYS_CSOR3 0x0
+#define CFG_SYS_AMASK3 IFC_AMASK(64*1024)
+#define CFG_SYS_CSOR3 0x0
/* CPLD Timing parameters for IFC CS3 */
-#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
+#define CFG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
FTIM0_GPCM_TEADC(0x0e) | \
FTIM0_GPCM_TEAHC(0x0e))
-#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
+#define CFG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
FTIM1_GPCM_TRAD(0x1f))
-#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
+#define CFG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
FTIM2_GPCM_TCH(0x8) | \
FTIM2_GPCM_TWP(0x1f))
-#define CONFIG_SYS_CS3_FTIM3 0x0
+#define CFG_SYS_CS3_FTIM3 0x0
-#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */
+#define CFG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
+#define CFG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/*
* Config the L2 Cache as L2 SRAM
*/
#if defined(CONFIG_SPL_BUILD)
#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
-#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
-#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CFG_SYS_INIT_L2_ADDR 0xD0000000
+#define CFG_SYS_INIT_L2_ADDR_PHYS CFG_SYS_INIT_L2_ADDR
+#define CFG_SYS_INIT_L2_END (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
#elif defined(CONFIG_MTD_RAW_NAND)
#ifdef CONFIG_TPL_BUILD
-#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
-#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CFG_SYS_INIT_L2_ADDR 0xD0000000
+#define CFG_SYS_INIT_L2_ADDR_PHYS CFG_SYS_INIT_L2_ADDR
+#define CFG_SYS_INIT_L2_END (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
#else
-#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
-#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CFG_SYS_INIT_L2_ADDR 0xD0000000
+#define CFG_SYS_INIT_L2_ADDR_PHYS CFG_SYS_INIT_L2_ADDR
+#define CFG_SYS_INIT_L2_END (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
#endif
#endif
#endif
@@ -324,11 +324,11 @@
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CFG_SYS_NS16550_CLK get_bus_freq(0)
-#define CONFIG_SYS_BAUDRATE_TABLE \
+#define CFG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
-#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
+#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x4500)
+#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x4600)
/* I2C */
#define I2C_PCA9557_ADDR1 0x18
@@ -343,7 +343,7 @@
/* RTC */
#define CONFIG_RTC_PT7C4338
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+#define CFG_SYS_I2C_RTC_ADDR 0x68
/*
* SPI interface will not be available in case of NAND boot SPI CS0 will be
@@ -393,7 +393,7 @@
*/
#if defined(CONFIG_MTD_RAW_NAND)
#ifdef CONFIG_TPL_BUILD
-#define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
+#define SPL_ENV_ADDR (CFG_SYS_INIT_L2_ADDR + (160 << 10))
#endif
#endif
@@ -410,7 +410,7 @@
* have to be in the first 64 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
+#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
/*
* Environment Configuration