global: Move remaining CONFIG_SYS_* to CFG_SYS_*
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do
not easily transition to Kconfig. In many cases they likely should come
from the device tree instead. Move these out of CONFIG namespace and in
to CFG namespace.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
diff --git a/include/configs/eb_cpu5282.h b/include/configs/eb_cpu5282.h
index 80de73d..426155d 100644
--- a/include/configs/eb_cpu5282.h
+++ b/include/configs/eb_cpu5282.h
@@ -12,7 +12,7 @@
* High Level Configuration Options (easy to change) *
*----------------------------------------------------------------------*/
-#define CONFIG_SYS_UART_PORT (0)
+#define CFG_SYS_UART_PORT (0)
#undef CONFIG_MONITOR_IS_IN_RAM /* starts uboot direct */
@@ -27,18 +27,18 @@
* Environment is in the second sector of the first 256k of flash *
*----------------------------------------------------------------------*/
-/*#define CONFIG_SYS_DRAM_TEST 1 */
-#undef CONFIG_SYS_DRAM_TEST
+/*#define CFG_SYS_DRAM_TEST 1 */
+#undef CFG_SYS_DRAM_TEST
/*----------------------------------------------------------------------*
* Clock and PLL Configuration *
*----------------------------------------------------------------------*/
-#define CONFIG_SYS_CLK 80000000 /* 8MHz * 8 */
+#define CFG_SYS_CLK 80000000 /* 8MHz * 8 */
/* PLL Configuration: Ext Clock * 8 (see table 9-4 of MCF user manual) */
-#define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */
-#define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */
+#define CFG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */
+#define CFG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */
/*----------------------------------------------------------------------*
* Network *
@@ -54,14 +54,14 @@
* You should know what you are doing if you make changes here.
*-----------------------------------------------------------------------*/
-#define CONFIG_SYS_MBAR 0x40000000
+#define CFG_SYS_MBAR 0x40000000
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*-----------------------------------------------------------------------*/
-#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
+#define CFG_SYS_INIT_RAM_ADDR 0x20000000
+#define CFG_SYS_INIT_RAM_SIZE 0x10000
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
@@ -79,34 +79,34 @@
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+#define CFG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CONFIG_FLASH_SHOW_PROGRESS 45
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
-#define CONFIG_SYS_INT_FLASH_BASE 0xF0000000
-#define CONFIG_SYS_INT_FLASH_ENABLE 0x21
+#define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE
+#define CFG_SYS_INT_FLASH_BASE 0xF0000000
+#define CFG_SYS_INT_FLASH_ENABLE 0x21
-#define CONFIG_SYS_FLASH_SIZE 16*1024*1024
+#define CFG_SYS_FLASH_SIZE 16*1024*1024
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE }
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM)
-#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
+#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE - 4)
+#define CFG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM)
+#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
+#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
CF_CACR_CEIB | CF_CACR_DBWE | \
CF_CACR_EUSP)
@@ -114,36 +114,36 @@
* Memory bank definitions
*/
-#define CONFIG_SYS_CS0_BASE 0xFF000000
-#define CONFIG_SYS_CS0_CTRL 0x00001980
-#define CONFIG_SYS_CS0_MASK 0x00FF0001
+#define CFG_SYS_CS0_BASE 0xFF000000
+#define CFG_SYS_CS0_CTRL 0x00001980
+#define CFG_SYS_CS0_MASK 0x00FF0001
-#define CONFIG_SYS_CS2_BASE 0xE0000000
-#define CONFIG_SYS_CS2_CTRL 0x00001980
-#define CONFIG_SYS_CS2_MASK 0x000F0001
+#define CFG_SYS_CS2_BASE 0xE0000000
+#define CFG_SYS_CS2_CTRL 0x00001980
+#define CFG_SYS_CS2_MASK 0x000F0001
-#define CONFIG_SYS_CS3_BASE 0xE0100000
-#define CONFIG_SYS_CS3_CTRL 0x00001980
-#define CONFIG_SYS_CS3_MASK 0x000F0001
+#define CFG_SYS_CS3_BASE 0xE0100000
+#define CFG_SYS_CS3_CTRL 0x00001980
+#define CFG_SYS_CS3_MASK 0x000F0001
/*-----------------------------------------------------------------------
* Port configuration
*/
-#define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */
-#define CONFIG_SYS_PADDR 0x0000000
-#define CONFIG_SYS_PADAT 0x0000000
+#define CFG_SYS_PACNT 0x0000000 /* Port A D[31:24] */
+#define CFG_SYS_PADDR 0x0000000
+#define CFG_SYS_PADAT 0x0000000
-#define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */
-#define CONFIG_SYS_PBDDR 0x0000000
-#define CONFIG_SYS_PBDAT 0x0000000
+#define CFG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */
+#define CFG_SYS_PBDDR 0x0000000
+#define CFG_SYS_PBDAT 0x0000000
-#define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */
+#define CFG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */
-#define CONFIG_SYS_PASPAR 0x0F0F
-#define CONFIG_SYS_PEHLPAR 0xC0
-#define CONFIG_SYS_PUAPAR 0x0F
-#define CONFIG_SYS_DDRUA 0x05
-#define CONFIG_SYS_PJPAR 0xFF
+#define CFG_SYS_PASPAR 0x0F0F
+#define CFG_SYS_PEHLPAR 0xC0
+#define CFG_SYS_PUAPAR 0x0F
+#define CFG_SYS_DDRUA 0x05
+#define CFG_SYS_PJPAR 0xFF
/*-----------------------------------------------------------------------
* I2C