| /* |
| * (C) Copyright 2002 |
| * Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
| * Marius Groeger <mgroeger@sysgo.de> |
| * |
| * (C) Copyright 2002 |
| * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> |
| * |
| * See file CREDITS for list of people who contributed to this |
| * project. |
| * |
| * This program is free software; you can redistribute it and/or |
| * modify it under the terms of the GNU General Public License as |
| * published by the Free Software Foundation; either version 2 of |
| * the License, or (at your option) any later version. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * You should have received a copy of the GNU General Public License |
| * along with this program; if not, write to the Free Software |
| * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| * MA 02111-1307 USA |
| */ |
| |
| /* |
| * CPU specific code |
| */ |
| |
| #include <common.h> |
| #include <command.h> |
| #include <arm920t.h> |
| #include <asm/system.h> |
| |
| #ifdef CONFIG_USE_IRQ |
| DECLARE_GLOBAL_DATA_PTR; |
| #endif |
| |
| static void cp_delay (void) |
| { |
| volatile int i; |
| |
| /* copro seems to need some delay between reading and writing */ |
| for (i = 0; i < 100; i++); |
| } |
| |
| int cpu_init (void) |
| { |
| /* |
| * setup up stacks if necessary |
| */ |
| #ifdef CONFIG_USE_IRQ |
| IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4; |
| FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; |
| #endif |
| return 0; |
| } |
| |
| int cleanup_before_linux (void) |
| { |
| /* |
| * this function is called just before we call linux |
| * it prepares the processor for linux |
| * |
| * we turn off caches etc ... |
| */ |
| |
| unsigned long i; |
| |
| disable_interrupts (); |
| |
| /* turn off I/D-cache */ |
| asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); |
| i &= ~(CR_C | CR_I); |
| asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); |
| |
| /* flush I/D-cache */ |
| i = 0; |
| asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); |
| |
| return (0); |
| } |
| |
| int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) |
| { |
| disable_interrupts (); |
| reset_cpu (0); |
| /*NOTREACHED*/ |
| return (0); |
| } |
| |
| void icache_enable (void) |
| { |
| ulong reg; |
| |
| reg = get_cr (); /* get control reg. */ |
| cp_delay (); |
| set_cr (reg | CR_I); |
| } |
| |
| void icache_disable (void) |
| { |
| ulong reg; |
| |
| reg = get_cr (); |
| cp_delay (); |
| set_cr (reg & ~CR_I); |
| } |
| |
| int icache_status (void) |
| { |
| return (get_cr () & CR_I) != 0; |
| } |
| |
| #ifdef USE_920T_MMU |
| /* It makes no sense to use the dcache if the MMU is not enabled */ |
| void dcache_enable (void) |
| { |
| ulong reg; |
| |
| reg = get_cr (); |
| cp_delay (); |
| set_cr (reg | CR_C); |
| } |
| |
| void dcache_disable (void) |
| { |
| ulong reg; |
| |
| reg = get_cr (); |
| cp_delay (); |
| reg &= ~CR_C; |
| set_cr (reg); |
| } |
| |
| int dcache_status (void) |
| { |
| return (get_cr () & CR_C) != 0; |
| } |
| #endif |