| /* |
| * (C) Copyright 2001 |
| * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| * |
| * Modified during 2001 by |
| * Advanced Communications Technologies (Australia) Pty. Ltd. |
| * Howard Walker, Tuong Vu-Dinh |
| * |
| * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com |
| * Added support for the 16M dram simm on the 8260ads boards |
| * |
| * See file CREDITS for list of people who contributed to this |
| * project. |
| * |
| * This program is free software; you can redistribute it and/or |
| * modify it under the terms of the GNU General Public License as |
| * published by the Free Software Foundation; either version 2 of |
| * the License, or (at your option) any later version. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * You should have received a copy of the GNU General Public License |
| * along with this program; if not, write to the Free Software |
| * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| * MA 02111-1307 USA |
| */ |
| |
| #include <common.h> |
| #include <ioports.h> |
| #include <mpc8260.h> |
| |
| /* |
| * I/O Port configuration table |
| * |
| * if conf is 1, then that port pin will be configured at boot time |
| * according to the five values podr/pdir/ppar/psor/pdat for that entry |
| */ |
| |
| const iop_conf_t iop_conf_tab[4][32] = { |
| |
| /* Port A configuration */ |
| { /* conf ppar psor pdir podr pdat */ |
| /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */ |
| /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */ |
| /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */ |
| /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */ |
| /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */ |
| /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */ |
| /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ |
| /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ |
| /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ |
| /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ |
| /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ |
| /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ |
| /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ |
| /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ |
| /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ |
| /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ |
| /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ |
| /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ |
| /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ |
| /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ |
| /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ |
| /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ |
| /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */ |
| /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */ |
| /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ |
| /* PA6 */ { 1, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */ |
| /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ |
| /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ |
| /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ |
| /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ |
| /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */ |
| /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ |
| }, |
| |
| /* Port B configuration */ |
| { /* conf ppar psor pdir podr pdat */ |
| /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ |
| /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ |
| /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ |
| /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ |
| /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ |
| /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ |
| /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ |
| /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ |
| /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ |
| /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ |
| /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ |
| /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ |
| /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ |
| /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ |
| /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ |
| /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ |
| /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ |
| /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ |
| /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */ |
| /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ |
| /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ |
| /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ |
| /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ |
| /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ |
| /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ |
| /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ |
| /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ |
| /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ |
| /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
| /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
| /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
| /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ |
| }, |
| |
| /* Port C */ |
| { /* conf ppar psor pdir podr pdat */ |
| /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ |
| /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ |
| /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ |
| /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ |
| /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ |
| /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ |
| /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ |
| /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ |
| /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ |
| /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ |
| /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ |
| /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ |
| /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */ |
| /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */ |
| /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ |
| /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */ |
| /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */ |
| /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ |
| /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ |
| /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ |
| /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ |
| /* PC10 */ { 1, 1, 0, 0, 0, 0 }, /* LXT970 FETHMDC */ |
| /* PC9 */ { 1, 1, 0, 0, 0, 0 }, /* LXT970 FETHMDIO */ |
| /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ |
| /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ |
| /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ |
| /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ |
| /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ |
| /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ |
| /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ |
| /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ |
| /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ |
| }, |
| |
| /* Port D */ |
| { /* conf ppar psor pdir podr pdat */ |
| /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ |
| /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ |
| /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ |
| /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */ |
| /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */ |
| /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ |
| /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ |
| /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ |
| /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ |
| /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ |
| /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ |
| /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ |
| /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ |
| /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ |
| /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ |
| /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ |
| /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ |
| /* PD14 */ { 1, 0, 0, 1, 0, 0 }, /* LED */ |
| /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ |
| /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ |
| /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ |
| /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ |
| /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ |
| /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ |
| /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ |
| /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ |
| /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ |
| /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ |
| /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
| /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
| /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
| /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ |
| } |
| }; |
| |
| typedef struct bscr_ { |
| unsigned long bcsr0; |
| unsigned long bcsr1; |
| unsigned long bcsr2; |
| unsigned long bcsr3; |
| unsigned long bcsr4; |
| unsigned long bcsr5; |
| unsigned long bcsr6; |
| unsigned long bcsr7; |
| } bcsr_t; |
| |
| void reset_phy(void) |
| { |
| volatile bcsr_t *bcsr = (bcsr_t *)CFG_BCSR; |
| |
| /* reset the FEC port */ |
| bcsr->bcsr1 &= ~FETH_RST; |
| bcsr->bcsr1 |= FETH_RST; |
| } |
| |
| |
| int board_pre_init (void) |
| { |
| volatile bcsr_t *bcsr = (bcsr_t *)CFG_BCSR; |
| bcsr->bcsr1 = ~FETHIEN & ~RS232EN_1; |
| |
| return 0; |
| } |
| |
| long int initdram(int board_type) |
| { |
| volatile immap_t *immap = (immap_t *)CFG_IMMR; |
| volatile memctl8260_t *memctl = &immap->im_memctl; |
| volatile uchar *ramaddr, |
| c = 0xff; |
| int i; |
| |
| #ifndef CFG_RAMBOOT |
| immap->im_siu_conf.sc_ppc_acr = 0x00000002; |
| immap->im_siu_conf.sc_ppc_alrh = 0x01267893; |
| immap->im_siu_conf.sc_tescr1 = 0x00004000; |
| |
| /* init local sdram, bank 4 */ |
| memctl->memc_lsrt = 0x00000010; |
| memctl->memc_or4 = 0xFFC01480; |
| memctl->memc_br4 = 0x04001861; |
| memctl->memc_lsdmr = 0x2886A522; |
| ramaddr = (uchar *)CFG_LSDRAM_BASE; |
| *ramaddr = c; |
| memctl->memc_lsdmr = 0x0886A522; |
| for( i = 0; i < 8; i++ ) { |
| *ramaddr = c; |
| } |
| memctl->memc_lsdmr = 0x1886A522; |
| *ramaddr = c; |
| memctl->memc_lsdmr = 0x4086A522; |
| |
| /* init sdram dimm */ |
| ramaddr = (uchar *)CFG_SDRAM_BASE; |
| memctl->memc_psrt = 0x00000010; |
| immap->im_memctl.memc_or2 = 0xFF000CA0; |
| immap->im_memctl.memc_br2 = 0x00000041; |
| memctl->memc_psdmr = 0x296EB452; |
| *ramaddr = c; |
| memctl->memc_psdmr = 0x096EB452; |
| for (i = 0; i < 8; i++) |
| *ramaddr = c; |
| |
| memctl->memc_psdmr = 0x196EB452; |
| *ramaddr = c; |
| memctl->memc_psdmr = 0x416EB452; |
| *ramaddr = c; |
| #endif |
| |
| /* return total ram size of simm */ |
| return (16 * 1024 * 1024); |
| } |
| |
| int checkboard(void) |
| { |
| puts ("Board: Motorola MPC8260ADS\n"); |
| return 0; |
| } |
| |