| // SPDX-License-Identifier: BSD-3-Clause |
| /* |
| * Clock drivers for Qualcomm SDM845 |
| * |
| * (C) Copyright 2017 Jorge Ramirez Ortiz <jorge.ramirez-ortiz@linaro.org> |
| * (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com> |
| * |
| * Based on Little Kernel driver, simplified |
| */ |
| |
| #include <common.h> |
| #include <clk-uclass.h> |
| #include <dm.h> |
| #include <linux/delay.h> |
| #include <errno.h> |
| #include <asm/io.h> |
| #include <linux/bitops.h> |
| #include <dt-bindings/clock/qcom,gcc-sdm845.h> |
| |
| #include "clock-qcom.h" |
| |
| #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } |
| |
| struct freq_tbl { |
| uint freq; |
| uint src; |
| u8 pre_div; |
| u16 m; |
| u16 n; |
| }; |
| |
| static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { |
| F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625), |
| F(14745600, CFG_CLK_SRC_GPLL0_EVEN, 1, 768, 15625), |
| F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0), |
| F(29491200, CFG_CLK_SRC_GPLL0_EVEN, 1, 1536, 15625), |
| F(32000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 75), |
| F(48000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 25), |
| F(64000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 16, 75), |
| F(80000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 15), |
| F(96000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 25), |
| F(100000000, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0), |
| F(102400000, CFG_CLK_SRC_GPLL0_EVEN, 1, 128, 375), |
| F(112000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 28, 75), |
| F(117964800, CFG_CLK_SRC_GPLL0_EVEN, 1, 6144, 15625), |
| F(120000000, CFG_CLK_SRC_GPLL0_EVEN, 2.5, 0, 0), |
| F(128000000, CFG_CLK_SRC_GPLL0, 1, 16, 75), |
| { } |
| }; |
| |
| static const struct bcr_regs uart2_regs = { |
| .cfg_rcgr = SE9_UART_APPS_CFG_RCGR, |
| .cmd_rcgr = SE9_UART_APPS_CMD_RCGR, |
| .M = SE9_UART_APPS_M, |
| .N = SE9_UART_APPS_N, |
| .D = SE9_UART_APPS_D, |
| }; |
| |
| const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, uint rate) |
| { |
| if (!f) |
| return NULL; |
| |
| if (!f->freq) |
| return f; |
| |
| for (; f->freq; f++) |
| if (rate <= f->freq) |
| return f; |
| |
| /* Default to our fastest rate */ |
| return f - 1; |
| } |
| |
| ulong msm_set_rate(struct clk *clk, ulong rate) |
| { |
| struct msm_clk_priv *priv = dev_get_priv(clk->dev); |
| const struct freq_tbl *freq; |
| |
| switch (clk->id) { |
| case GCC_QUPV3_WRAP1_S1_CLK: /* UART9 */ |
| freq = qcom_find_freq(ftbl_gcc_qupv3_wrap0_s0_clk_src, rate); |
| clk_rcg_set_rate_mnd(priv->base, &uart2_regs, |
| freq->pre_div, freq->m, freq->n, freq->src); |
| |
| return freq->freq; |
| default: |
| return 0; |
| } |
| } |
| |
| static const struct gate_clk sdm845_clks[] = { |
| GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x5200c, 0x00000400), |
| GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x5200c, 0x00000800), |
| GATE_CLK(GCC_QUPV3_WRAP0_S2_CLK, 0x5200c, 0x00001000), |
| GATE_CLK(GCC_QUPV3_WRAP0_S3_CLK, 0x5200c, 0x00002000), |
| GATE_CLK(GCC_QUPV3_WRAP0_S4_CLK, 0x5200c, 0x00004000), |
| GATE_CLK(GCC_QUPV3_WRAP0_S5_CLK, 0x5200c, 0x00008000), |
| GATE_CLK(GCC_QUPV3_WRAP0_S6_CLK, 0x5200c, 0x00010000), |
| GATE_CLK(GCC_QUPV3_WRAP0_S7_CLK, 0x5200c, 0x00020000), |
| GATE_CLK(GCC_QUPV3_WRAP1_S0_CLK, 0x5200c, 0x00400000), |
| GATE_CLK(GCC_QUPV3_WRAP1_S1_CLK, 0x5200c, 0x00800000), |
| GATE_CLK(GCC_QUPV3_WRAP1_S3_CLK, 0x5200c, 0x02000000), |
| GATE_CLK(GCC_QUPV3_WRAP1_S4_CLK, 0x5200c, 0x04000000), |
| GATE_CLK(GCC_QUPV3_WRAP1_S5_CLK, 0x5200c, 0x08000000), |
| GATE_CLK(GCC_QUPV3_WRAP1_S6_CLK, 0x5200c, 0x10000000), |
| GATE_CLK(GCC_QUPV3_WRAP1_S7_CLK, 0x5200c, 0x20000000), |
| GATE_CLK(GCC_QUPV3_WRAP_0_M_AHB_CLK, 0x5200c, 0x00000040), |
| GATE_CLK(GCC_QUPV3_WRAP_0_S_AHB_CLK, 0x5200c, 0x00000080), |
| GATE_CLK(GCC_QUPV3_WRAP_1_M_AHB_CLK, 0x5200c, 0x00100000), |
| GATE_CLK(GCC_QUPV3_WRAP_1_S_AHB_CLK, 0x5200c, 0x00200000), |
| GATE_CLK(GCC_SDCC2_AHB_CLK, 0x14008, 0x00000001), |
| GATE_CLK(GCC_SDCC2_APPS_CLK, 0x14004, 0x00000001), |
| GATE_CLK(GCC_SDCC4_AHB_CLK, 0x16008, 0x00000001), |
| GATE_CLK(GCC_SDCC4_APPS_CLK, 0x16004, 0x00000001), |
| GATE_CLK(GCC_UFS_CARD_AHB_CLK, 0x75010, 0x00000001), |
| GATE_CLK(GCC_UFS_CARD_AXI_CLK, 0x7500c, 0x00000001), |
| GATE_CLK(GCC_UFS_CARD_CLKREF_CLK, 0x8c004, 0x00000001), |
| GATE_CLK(GCC_UFS_CARD_ICE_CORE_CLK, 0x75058, 0x00000001), |
| GATE_CLK(GCC_UFS_CARD_PHY_AUX_CLK, 0x7508c, 0x00000001), |
| GATE_CLK(GCC_UFS_CARD_RX_SYMBOL_0_CLK, 0x75018, 0x00000001), |
| GATE_CLK(GCC_UFS_CARD_RX_SYMBOL_1_CLK, 0x750a8, 0x00000001), |
| GATE_CLK(GCC_UFS_CARD_TX_SYMBOL_0_CLK, 0x75014, 0x00000001), |
| GATE_CLK(GCC_UFS_CARD_UNIPRO_CORE_CLK, 0x75054, 0x00000001), |
| GATE_CLK(GCC_UFS_MEM_CLKREF_CLK, 0x8c000, 0x00000001), |
| GATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x77010, 0x00000001), |
| GATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x7700c, 0x00000001), |
| GATE_CLK(GCC_UFS_PHY_ICE_CORE_CLK, 0x77058, 0x00000001), |
| GATE_CLK(GCC_UFS_PHY_PHY_AUX_CLK, 0x7708c, 0x00000001), |
| GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_0_CLK, 0x77018, 0x00000001), |
| GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_1_CLK, 0x770a8, 0x00000001), |
| GATE_CLK(GCC_UFS_PHY_TX_SYMBOL_0_CLK, 0x77014, 0x00000001), |
| GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x77054, 0x00000001), |
| GATE_CLK(GCC_USB30_PRIM_MASTER_CLK, 0x0f00c, 0x00000001), |
| GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0x0f014, 0x00000001), |
| GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK, 0x0f010, 0x00000001), |
| GATE_CLK(GCC_USB30_SEC_MASTER_CLK, 0x1000c, 0x00000001), |
| GATE_CLK(GCC_USB30_SEC_MOCK_UTMI_CLK, 0x10014, 0x00000001), |
| GATE_CLK(GCC_USB30_SEC_SLEEP_CLK, 0x10010, 0x00000001), |
| GATE_CLK(GCC_USB3_PRIM_CLKREF_CLK, 0x8c008, 0x00000001), |
| GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0x0f04c, 0x00000001), |
| GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0x0f050, 0x00000001), |
| GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0x0f054, 0x00000001), |
| GATE_CLK(GCC_USB3_SEC_CLKREF_CLK, 0x8c028, 0x00000001), |
| GATE_CLK(GCC_USB3_SEC_PHY_AUX_CLK, 0x1004c, 0x00000001), |
| GATE_CLK(GCC_USB3_SEC_PHY_PIPE_CLK, 0x10054, 0x00000001), |
| GATE_CLK(GCC_USB3_SEC_PHY_COM_AUX_CLK, 0x10050, 0x00000001), |
| GATE_CLK(GCC_USB_PHY_CFG_AHB2PHY_CLK, 0x6a004, 0x00000001), |
| }; |
| |
| int msm_enable(struct clk *clk) |
| { |
| struct msm_clk_priv *priv = dev_get_priv(clk->dev); |
| |
| debug("%s: clk %s\n", __func__, sdm845_clks[clk->id].name); |
| |
| qcom_gate_clk_en(priv, clk->id); |
| |
| return 0; |
| } |
| |
| static const struct qcom_reset_map sdm845_gcc_resets[] = { |
| [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 }, |
| [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 }, |
| [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, |
| [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, |
| [GCC_SDCC2_BCR] = { 0x14000 }, |
| [GCC_SDCC4_BCR] = { 0x16000 }, |
| [GCC_UFS_CARD_BCR] = { 0x75000 }, |
| [GCC_UFS_PHY_BCR] = { 0x77000 }, |
| [GCC_USB30_PRIM_BCR] = { 0xf000 }, |
| [GCC_USB30_SEC_BCR] = { 0x10000 }, |
| [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 }, |
| [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 }, |
| [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 }, |
| [GCC_USB3_PHY_SEC_BCR] = { 0x5000c }, |
| [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 }, |
| [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 }, |
| [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, |
| }; |
| |
| static const struct msm_clk_data qcs404_gcc_data = { |
| .resets = sdm845_gcc_resets, |
| .num_resets = ARRAY_SIZE(sdm845_gcc_resets), |
| .clks = sdm845_clks, |
| .num_clks = ARRAY_SIZE(sdm845_clks), |
| }; |
| |
| static const struct udevice_id gcc_sdm845_of_match[] = { |
| { |
| .compatible = "qcom,gcc-sdm845", |
| .data = (ulong)&qcs404_gcc_data, |
| }, |
| { } |
| }; |
| |
| U_BOOT_DRIVER(gcc_sdm845) = { |
| .name = "gcc_sdm845", |
| .id = UCLASS_NOP, |
| .of_match = gcc_sdm845_of_match, |
| .bind = qcom_cc_bind, |
| .flags = DM_FLAG_PRE_RELOC, |
| }; |