rename CFG_ macros to CONFIG_SYS
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
diff --git a/board/freescale/m5249evb/m5249evb.c b/board/freescale/m5249evb/m5249evb.c
index c9ed341..b1ccbeb 100644
--- a/board/freescale/m5249evb/m5249evb.c
+++ b/board/freescale/m5249evb/m5249evb.c
@@ -42,7 +42,7 @@
/*
* Set LED on
*/
- val = mbar2_readLong(MCFSIM_GPIO1_OUT) & ~CFG_GPIO1_LED;
+ val = mbar2_readLong(MCFSIM_GPIO1_OUT) & ~CONFIG_SYS_GPIO1_LED;
mbar2_writeLong(MCFSIM_GPIO1_OUT, val); /* Set LED on */
return 0;
@@ -57,13 +57,13 @@
* RC = ([(RefreshTime/#rows) / (1/BusClk)] / 16) - 1
*/
-#ifdef CFG_FAST_CLK
+#ifdef CONFIG_SYS_FAST_CLK
/*
* Busclk=70MHz, RefreshTime=64ms, #rows=4096 (4K)
* SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=39
*/
mbar_writeShort(MCFSIM_DCR, 0x8239);
-#elif CFG_PLL_BYPASS
+#elif CONFIG_SYS_PLL_BYPASS
/*
* Busclk=5.6448MHz, RefreshTime=64ms, #rows=8192 (8K)
* SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=02
@@ -101,7 +101,7 @@
mbar_writeLong(MCFSIM_DACR0, 0x0000b364); /* Enable DACR0[IMRS] (bit 6); RE remains enabled */
*((volatile unsigned long *) 0x800) = junk; /* Access RAM to initialize the mode register */
- return CFG_SDRAM_SIZE * 1024 * 1024;
+ return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
};