| /* |
| * (C) Copyright 2016 Rockchip Electronics Co., Ltd |
| * |
| * SPDX-License-Identifier: GPL-2.0+ |
| */ |
| #ifndef __CONFIG_RV1108_COMMON_H |
| #define __CONFIG_RV1108_COMMON_H |
| |
| #include <asm/arch/hardware.h> |
| #include "rockchip-common.h" |
| |
| #define CONFIG_ENV_SIZE 0x2000 |
| #define CONFIG_SYS_MALLOC_LEN (32 << 20) |
| #define CONFIG_SYS_CBSIZE 1024 |
| #define CONFIG_SKIP_LOWLEVEL_INIT |
| |
| #define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) |
| /* TIMER1,initialized by ddr initialize code */ |
| #define CONFIG_SYS_TIMER_BASE 0x10350020 |
| #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) |
| |
| #define CONFIG_SYS_NS16550 |
| #define CONFIG_SYS_NS16550_MEM32 |
| |
| #define CONFIG_SYS_SDRAM_BASE 0x60000000 |
| #define CONFIG_NR_DRAM_BANKS 1 |
| #define CONFIG_SYS_TEXT_BASE CONFIG_SYS_SDRAM_BASE |
| #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x100000) |
| #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x2000000) |
| |
| #endif |