mips: mtmips: add two reference boards for mt7620
The mt7620_rfb board supports integrated 10/100M PHYs plus two external
giga PHYs. It also has 8MB SPI-NOR, mini PCI-e x1 slot, SDHC and USB.
The mt7620_mt7530_rfb boards supports an external MT7530 giga switch and a
16MB SPI-NOR flash.
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
diff --git a/arch/mips/dts/mediatek,mt7620-rfb.dts b/arch/mips/dts/mediatek,mt7620-rfb.dts
new file mode 100644
index 0000000..616903e
--- /dev/null
+++ b/arch/mips/dts/mediatek,mt7620-rfb.dts
@@ -0,0 +1,97 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 MediaTek Inc.
+ *
+ * Author: Weijie Gao <weijie.gao@mediatek.com>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include "mt7620.dtsi"
+
+/ {
+ compatible = "mediatek,mt7620-rfb", "mediatek,mt7620-soc";
+ model = "MediaTek MT7620 RFB (WS2120)";
+
+ aliases {
+ serial0 = &uartlite;
+ spi0 = &spi0;
+ };
+
+ chosen {
+ stdout-path = &uartlite;
+ };
+};
+
+&uartlite {
+ status = "okay";
+};
+
+&pinctrl {
+ state_default: pin_state {
+ pleds {
+ groups = "ephy led", "wled";
+ function = "led";
+ };
+
+ gpios {
+ groups = "uartf";
+ function = "gpio";
+ };
+ };
+
+ gsw_pins: gsw_pins {
+ mdio {
+ groups = "mdio";
+ function = "mdio";
+ };
+
+ rgmii1 {
+ groups = "rgmii1";
+ function = "rgmii1";
+ };
+
+ rgmii2 {
+ groups = "rgmii2";
+ function = "rgmii2";
+ };
+ };
+};
+
+&spi0 {
+ status = "okay";
+ num-cs = <2>;
+
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <25000000>;
+ reg = <0>;
+ };
+};
+
+ð {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&gsw_pins>;
+
+ port4 {
+ phy-mode = "rgmii";
+ phy-addr = <4>;
+ };
+
+ port5 {
+ phy-mode = "rgmii";
+ phy-addr = <5>;
+ };
+};
+
+&mmc {
+ bus-width = <4>;
+ cap-sd-highspeed;
+
+ status = "okay";
+};