board/ttcontrol/vision2/imximage_hynix.cfg - platform/external/u-boot - Gitiles

 #
 # (C) Copyright 2009
 # Stefano Babic DENX Software Engineering sbabic@denx.de.
 #
 # (C) Copyright 2010
 # Klaus Steinhammer TTECH Control Gmbh kst@tttech.com
 #
 # See file CREDITS for list of people who contributed to this
 # project.
 #
 # This program is free software; you can redistribute it and/or
 # modify it under the terms of the GNU General Public License as
 # published by the Free Software Foundation; either version 2 of
 # the License or (at your option) any later version.
 #
 # This program is distributed in the hope that it will be useful,
 # but WITHOUT ANY WARRANTY; without even the implied warranty of
 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 # GNU General Public License for more details.
 #
 # You should have received a copy of the GNU General Public License
 # along with this program; if not write to the Free Software
 # Foundation Inc. 51 Franklin Street Fifth Floor Boston,
 # MA 02110-1301 USA
 #
 # Refer docs/README.imxmage for more details about how-to configure
 # and create imximage boot image
 #
 # The syntax is taken as close as possible with the kwbimage

 # Boot Device : one of
 # spi, nand, onenand, sd

 BOOT_FROM	spi

 # Device Configuration Data (DCD)
 #
 # Each entry must have the format:
 # Addr-type           Address        Value
 #
 # where:
 #	Addr-type register length (1,2 or 4 bytes)
 #	Address	  absolute address of the register
 #	value	  value to be stored in the register

 #######################
 ### Disable WDOG ###
 #######################
 DATA 2 0x73f98000 0x30

 #######################
 ### SET DDR Clk     ###
 #######################

 # CCM: CBMCR - ddr_clk_sel: axi_b (133MHz)
 DATA 4 0x73FD4018 0x000024C0

 # DOUBLE SPI CLK (13MHz->26 MHz Clock)
 DATA 4 0x73FD4038 0x2010241

 #IOMUXC_SW_PAD_CTL_PAD_CSPI1_MOSI HYS_ENABLE | DRV_MAX | SRE_FAST
 DATA 4 0x73fa8600 0x00000107
 #IOMUXC_SW_PAD_CTL_PAD_CSPI1_MISO HYS_ENABLE | DRV_MAX | SRE_FAST
 DATA 4 0x73fa8604 0x00000107
 #IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS0 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST
 DATA 4 0x73fa8608 0x00000187
 #IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS1 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST
 DATA 4 0x73fa860c 0x00000187
 #IOMUXC_SW_PAD_CTL_PAD_CSPI1_SCLK HYS_ENABLE | DRV_MAX | SRE_FAST
 DATA 4 0x73fa8614 0x00000107
 #IOMUXC_SW_PAD_CTL_PAD_DI1_PIN11 HYS_ENABLE | DRV_MAX | SRE_FAST (CSPI1_SS2)
 DATA 4 0x73fa86a8 0x00000187

 #######################
 ### Settings IOMUXC ###
 #######################

 # DDR IOMUX configuration
 # Control, Data, Address pads are in their default state: HIGH DS, FAST SR.
 # IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK MAX DS
 DATA 4 0x73fa84b8 0x000000e7
 # PVTC MAX (at GPC, PGR reg)
 #DATA 4 0x73FD8004 0x1fc00000

 #DQM0 DS high slew rate slow
 DATA 4 0x73fa84d4 0x000000e4
 #DQM1 DS high slew rate slow
 DATA 4 0x73fa84d8 0x000000e4
 #DQM2 DS high slew rate slow
 DATA 4 0x73fa84dc 0x000000e4
 #DQM3 DS high slew rate slow
 DATA 4 0x73fa84e0 0x000000e4

 #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 DS high & SLEW slow
 DATA 4 0x73fa84bc 0x000000c4
 #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 DS high & SLEW slow
 DATA 4 0x73fa84c0 0x000000c4
 #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 DS high & SLEW slow
 DATA 4 0x73fa84c4 0x000000c4
 #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 DS high & SLEW slow
 DATA 4 0x73fa84c8 0x000000c4

 #DRAM_DATA B0
 DATA 4 0x73fa88a4 0x00000004
 #DRAM_DATA B1
 DATA 4 0x73fa88ac 0x00000004
 #DRAM_DATA B2
 DATA 4 0x73fa88b8 0x00000004
 #DRAM_DATA B3
 DATA 4 0x73fa882c 0x00000004

 #DRAM_DATA B0 slew rate
 DATA 4 0x73fa8878 0x00000000
 #DRAM_DATA B1 slew rate
 DATA 4 0x73fa8880 0x00000000
 #DRAM_DATA B2 slew rate
 DATA 4 0x73fa888c 0x00000000
 #DRAM_DATA B3 slew rate
 DATA 4 0x73fa889c 0x00000000

 #######################
 ### Configure SDRAM ###
 #######################

 # Configure CS0
 #######################

 # ESDCTL0: Enable controller
 DATA 4 0x83fd9000 0x83220000

 # Init DRAM on CS0
 # ESDSCR: Precharge command
 DATA 4 0x83fd9014 0x04008008
 # ESDSCR: Refresh command
 DATA 4 0x83fd9014 0x00008010
 # ESDSCR: Refresh command
 DATA 4 0x83fd9014 0x00008010
 # ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8)
 DATA 4 0x83fd9014 0x00338018
 # ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51)
 DATA 4 0x83fd9014 0x0020801a
 # ESDSCR
 DATA 4 0x83fd9014 0x00008000

 # ESDSCR: EMR with full Drive strength
 #DATA 4 0x83fd9014 0x0000801a

 # ESDCTL0: 14 ROW, 10 COL, 32Bit, SREF=8
 DATA 4 0x83fd9000 0xC3220000

 # ESDCFG0: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks
 #          tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks
 #DATA 4 0x83fd9004 0xC33574AA

 #micron mDDR
 # ESDCFG0: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks
 # tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
 #DATA 4 0x83FD9004 0x101564a8

 #hynix mDDR
 # ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks
 # tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
 DATA 4 0x83FD9004 0x704564a8

 # ESDMISC: AP=10, Bank interleaving on, MIF3 en, RALAT=2
 DATA 4 0x83fd9010 0x000a1700

 # Configure CS1
 #######################

 # ESDCTL1: Enable controller
 DATA 4 0x83fd9008 0x83220000

 # Init DRAM on CS1
 # ESDSCR: Precharge command
 DATA 4 0x83fd9014 0x0400800c
 # ESDSCR: Refresh command
 DATA 4 0x83fd9014 0x00008014
 # ESDSCR: Refresh command
 DATA 4 0x83fd9014 0x00008014
 # ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8)
 DATA 4 0x83fd9014 0x0033801c
 # ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51)
 DATA 4 0x83fd9014 0x0020801e
 # ESDSCR
 DATA 4 0x83fd9014 0x00008004

 # ESDCTL1: 14 ROW, 10 COL, 32Bit, SREF=8
 DATA 4 0x83fd9008 0xC3220000

 # ESDCFG1: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks
 #          tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks
 #DATA 4 0x83fd900c 0xC33574AA

 #micron mDDR
 # ESDCFG1: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks
 # tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
 #DATA 4 0x83FD900C 0x101564a8

 #hynix mDDR
 # ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks
 # tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
 DATA 4 0x83FD900C 0x704564a8

 # ESDSCR (mDRAM configuration finished)
 DATA 4 0x83FD9014 0x00000004

 # ESDSCR - clear "configuration request" bit
 DATA 4 0x83fd9014 0x00000000
	#
	# (C) Copyright 2009
	# Stefano Babic DENX Software Engineering sbabic@denx.de.
	#
	# (C) Copyright 2010
	# Klaus Steinhammer TTECH Control Gmbh kst@tttech.com
	#
	# See file CREDITS for list of people who contributed to this
	# project.
	#
	# This program is free software; you can redistribute it and/or
	# modify it under the terms of the GNU General Public License as
	# published by the Free Software Foundation; either version 2 of
	# the License or (at your option) any later version.
	#
	# This program is distributed in the hope that it will be useful,
	# but WITHOUT ANY WARRANTY; without even the implied warranty of
	# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	# GNU General Public License for more details.
	#
	# You should have received a copy of the GNU General Public License
	# along with this program; if not write to the Free Software
	# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
	# MA 02110-1301 USA
	#
	# Refer docs/README.imxmage for more details about how-to configure
	# and create imximage boot image
	#
	# The syntax is taken as close as possible with the kwbimage

	# Boot Device : one of
	# spi, nand, onenand, sd

	BOOT_FROM spi

	# Device Configuration Data (DCD)
	#
	# Each entry must have the format:
	# Addr-type Address Value
	#
	# where:
	# Addr-type register length (1,2 or 4 bytes)
	# Address absolute address of the register
	# value value to be stored in the register

	#######################
	### Disable WDOG ###
	#######################
	DATA 2 0x73f98000 0x30

	#######################
	### SET DDR Clk ###
	#######################

	# CCM: CBMCR - ddr_clk_sel: axi_b (133MHz)
	DATA 4 0x73FD4018 0x000024C0

	# DOUBLE SPI CLK (13MHz->26 MHz Clock)
	DATA 4 0x73FD4038 0x2010241

	#IOMUXC_SW_PAD_CTL_PAD_CSPI1_MOSI HYS_ENABLE \| DRV_MAX \| SRE_FAST
	DATA 4 0x73fa8600 0x00000107
	#IOMUXC_SW_PAD_CTL_PAD_CSPI1_MISO HYS_ENABLE \| DRV_MAX \| SRE_FAST
	DATA 4 0x73fa8604 0x00000107
	#IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS0 HYS_ENABLE \| PKE_ENABLE \| DRV_MAX \| SRE_FAST
	DATA 4 0x73fa8608 0x00000187
	#IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS1 HYS_ENABLE \| PKE_ENABLE \| DRV_MAX \| SRE_FAST
	DATA 4 0x73fa860c 0x00000187
	#IOMUXC_SW_PAD_CTL_PAD_CSPI1_SCLK HYS_ENABLE \| DRV_MAX \| SRE_FAST
	DATA 4 0x73fa8614 0x00000107
	#IOMUXC_SW_PAD_CTL_PAD_DI1_PIN11 HYS_ENABLE \| DRV_MAX \| SRE_FAST (CSPI1_SS2)
	DATA 4 0x73fa86a8 0x00000187

	#######################
	### Settings IOMUXC ###
	#######################

	# DDR IOMUX configuration
	# Control, Data, Address pads are in their default state: HIGH DS, FAST SR.
	# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK MAX DS
	DATA 4 0x73fa84b8 0x000000e7
	# PVTC MAX (at GPC, PGR reg)
	#DATA 4 0x73FD8004 0x1fc00000

	#DQM0 DS high slew rate slow
	DATA 4 0x73fa84d4 0x000000e4
	#DQM1 DS high slew rate slow
	DATA 4 0x73fa84d8 0x000000e4
	#DQM2 DS high slew rate slow
	DATA 4 0x73fa84dc 0x000000e4
	#DQM3 DS high slew rate slow
	DATA 4 0x73fa84e0 0x000000e4

	#IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 DS high & SLEW slow
	DATA 4 0x73fa84bc 0x000000c4
	#IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 DS high & SLEW slow
	DATA 4 0x73fa84c0 0x000000c4
	#IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 DS high & SLEW slow
	DATA 4 0x73fa84c4 0x000000c4
	#IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 DS high & SLEW slow
	DATA 4 0x73fa84c8 0x000000c4

	#DRAM_DATA B0
	DATA 4 0x73fa88a4 0x00000004
	#DRAM_DATA B1
	DATA 4 0x73fa88ac 0x00000004
	#DRAM_DATA B2
	DATA 4 0x73fa88b8 0x00000004
	#DRAM_DATA B3
	DATA 4 0x73fa882c 0x00000004

	#DRAM_DATA B0 slew rate
	DATA 4 0x73fa8878 0x00000000
	#DRAM_DATA B1 slew rate
	DATA 4 0x73fa8880 0x00000000
	#DRAM_DATA B2 slew rate
	DATA 4 0x73fa888c 0x00000000
	#DRAM_DATA B3 slew rate
	DATA 4 0x73fa889c 0x00000000

	#######################
	### Configure SDRAM ###
	#######################

	# Configure CS0
	#######################

	# ESDCTL0: Enable controller
	DATA 4 0x83fd9000 0x83220000

	# Init DRAM on CS0
	# ESDSCR: Precharge command
	DATA 4 0x83fd9014 0x04008008
	# ESDSCR: Refresh command
	DATA 4 0x83fd9014 0x00008010
	# ESDSCR: Refresh command
	DATA 4 0x83fd9014 0x00008010
	# ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8)
	DATA 4 0x83fd9014 0x00338018
	# ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51)
	DATA 4 0x83fd9014 0x0020801a
	# ESDSCR
	DATA 4 0x83fd9014 0x00008000

	# ESDSCR: EMR with full Drive strength
	#DATA 4 0x83fd9014 0x0000801a

	# ESDCTL0: 14 ROW, 10 COL, 32Bit, SREF=8
	DATA 4 0x83fd9000 0xC3220000

	# ESDCFG0: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks
	# tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks
	#DATA 4 0x83fd9004 0xC33574AA

	#micron mDDR
	# ESDCFG0: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks
	# tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
	#DATA 4 0x83FD9004 0x101564a8

	#hynix mDDR
	# ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks
	# tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
	DATA 4 0x83FD9004 0x704564a8

	# ESDMISC: AP=10, Bank interleaving on, MIF3 en, RALAT=2
	DATA 4 0x83fd9010 0x000a1700

	# Configure CS1
	#######################

	# ESDCTL1: Enable controller
	DATA 4 0x83fd9008 0x83220000

	# Init DRAM on CS1
	# ESDSCR: Precharge command
	DATA 4 0x83fd9014 0x0400800c
	# ESDSCR: Refresh command
	DATA 4 0x83fd9014 0x00008014
	# ESDSCR: Refresh command
	DATA 4 0x83fd9014 0x00008014
	# ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8)
	DATA 4 0x83fd9014 0x0033801c
	# ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51)
	DATA 4 0x83fd9014 0x0020801e
	# ESDSCR
	DATA 4 0x83fd9014 0x00008004

	# ESDCTL1: 14 ROW, 10 COL, 32Bit, SREF=8
	DATA 4 0x83fd9008 0xC3220000

	# ESDCFG1: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks
	# tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks
	#DATA 4 0x83fd900c 0xC33574AA

	#micron mDDR
	# ESDCFG1: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks
	# tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
	#DATA 4 0x83FD900C 0x101564a8

	#hynix mDDR
	# ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks
	# tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
	DATA 4 0x83FD900C 0x704564a8

	# ESDSCR (mDRAM configuration finished)
	DATA 4 0x83FD9014 0x00000004

	# ESDSCR - clear "configuration request" bit
	DATA 4 0x83fd9014 0x00000000