| // SPDX-License-Identifier: (GPL-2.0 OR MIT) |
| /* |
| * Copyright 2017 NXP |
| * Copyright (C) 2021 Ronetix, Ilko Iliev <iliev@ronetix.at> |
| */ |
| |
| /dts-v1/; |
| |
| #include "imx8mq.dtsi" |
| |
| / { |
| model = "Ronetix iMX8M-CM SoM"; |
| compatible = "ronetix,imx8mq-cm", "fsl,imx8mq"; |
| |
| chosen { |
| stdout-path = &uart1; |
| }; |
| |
| memory@40000000 { |
| device_type = "memory"; |
| reg = <0x00000000 0x40000000 0 0x40000000>; |
| }; |
| |
| pcie0_refclk: pcie0-refclk { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <100000000>; |
| }; |
| |
| pmic_osc: clock-pmic { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <32768>; |
| clock-output-names = "pmic_osc"; |
| }; |
| |
| osc_32k: clock-osc-32k { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <32768>; |
| clock-output-names = "osc_32k"; |
| }; |
| |
| reg_usdhc2_vmmc: regulator-vsd-3v3 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_reg_usdhc2>; |
| compatible = "regulator-fixed"; |
| regulator-name = "VSD_3V3"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| }; |
| }; |
| |
| &A53_0 { |
| cpu-supply = <&buck2_reg>; |
| }; |
| |
| &A53_1 { |
| cpu-supply = <&buck2_reg>; |
| }; |
| |
| &A53_2 { |
| cpu-supply = <&buck2_reg>; |
| }; |
| |
| &A53_3 { |
| cpu-supply = <&buck2_reg>; |
| }; |
| |
| &ddrc { |
| operating-points-v2 = <&ddrc_opp_table>; |
| |
| ddrc_opp_table: opp-table { |
| compatible = "operating-points-v2"; |
| |
| opp-25M { |
| opp-hz = /bits/ 64 <25000000>; |
| }; |
| |
| opp-100M { |
| opp-hz = /bits/ 64 <100000000>; |
| }; |
| |
| /* |
| * On imx8mq B0 PLL can't be bypassed so low bus is 166M |
| */ |
| opp-166M { |
| opp-hz = /bits/ 64 <166935483>; |
| }; |
| |
| opp-800M { |
| opp-hz = /bits/ 64 <800000000>; |
| }; |
| }; |
| }; |
| |
| &dphy { |
| status = "okay"; |
| }; |
| |
| &fec1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_fec1>; |
| phy-mode = "rgmii-id"; |
| phy-handle = <ðphy0>; |
| fsl,magic-packet; |
| status = "okay"; |
| |
| mdio { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| ethphy0: ethernet-phy@0 { |
| compatible = "ethernet-phy-ieee802.3-c22"; |
| reg = <0>; |
| reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; |
| reset-assert-us = <10000>; |
| }; |
| }; |
| }; |
| |
| &i2c1 { |
| clock-frequency = <100000>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_i2c1>; |
| status = "okay"; |
| }; |
| |
| &i2c2 { |
| clock-frequency = <100000>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_i2c2>; |
| status = "okay"; |
| |
| pmic@4b { |
| compatible = "rohm,bd71837"; |
| reg = <0x4b>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_pmic>; |
| interrupt-parent = <&gpio1>; |
| interrupts = <3 IRQ_TYPE_LEVEL_LOW>; |
| rohm,reset-snvs-powered; |
| |
| #clock-cells = <0>; |
| clocks = <&osc_32k 0>; |
| clock-output-names = "clk-32k-out"; |
| |
| regulators { |
| buck1_reg: BUCK1 { |
| regulator-name = "buck1"; |
| regulator-min-microvolt = <700000>; |
| regulator-max-microvolt = <1300000>; |
| regulator-boot-on; |
| regulator-always-on; |
| regulator-ramp-delay = <1250>; |
| }; |
| |
| buck2_reg: BUCK2 { |
| regulator-name = "buck2"; |
| regulator-min-microvolt = <700000>; |
| regulator-max-microvolt = <1300000>; |
| regulator-boot-on; |
| regulator-always-on; |
| regulator-ramp-delay = <1250>; |
| rohm,dvs-run-voltage = <1000000>; |
| rohm,dvs-idle-voltage = <900000>; |
| }; |
| |
| buck3_reg: BUCK3 { |
| // BUCK5 in datasheet |
| regulator-name = "buck3"; |
| regulator-min-microvolt = <700000>; |
| regulator-max-microvolt = <1350000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| buck4_reg: BUCK4 { |
| // BUCK6 in datasheet |
| regulator-name = "buck4"; |
| regulator-min-microvolt = <3000000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| buck5_reg: BUCK5 { |
| // BUCK7 in datasheet |
| regulator-name = "buck5"; |
| regulator-min-microvolt = <1605000>; |
| regulator-max-microvolt = <1995000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| buck6_reg: BUCK6 { |
| // BUCK8 in datasheet |
| regulator-name = "buck6"; |
| regulator-min-microvolt = <800000>; |
| regulator-max-microvolt = <1400000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| buck7_reg: BUCK7 { |
| regulator-name = "buck7"; |
| regulator-min-microvolt = <1605000>; |
| regulator-max-microvolt = <1995000>; |
| regulator-boot-on; |
| }; |
| |
| buck8_reg: BUCK8 { |
| regulator-name = "buck8"; |
| regulator-min-microvolt = <800000>; |
| regulator-max-microvolt = <1400000>; |
| regulator-boot-on; |
| }; |
| |
| ldo1_reg: LDO1 { |
| regulator-name = "ldo1"; |
| regulator-min-microvolt = <1600000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| ldo2_reg: LDO2 { |
| regulator-name = "ldo2"; |
| regulator-min-microvolt = <800000>; |
| regulator-max-microvolt = <900000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| ldo3_reg: LDO3 { |
| regulator-name = "ldo3"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| ldo4_reg: LDO4 { |
| regulator-name = "ldo4"; |
| regulator-min-microvolt = <900000>; |
| regulator-max-microvolt = <1800000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| ldo6_reg: LDO6 { |
| regulator-name = "ldo6"; |
| regulator-min-microvolt = <900000>; |
| regulator-max-microvolt = <1800000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| }; |
| }; |
| |
| i2c_eeprom: i2c_eeprom@50 { |
| compatible = "microchip,24lc512"; |
| reg = <0x50>; |
| pagesize = <128>; |
| }; |
| }; |
| |
| &lcdif { |
| status = "okay"; |
| }; |
| |
| &pcie0 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_pcie0>; |
| reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>; |
| clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, |
| <&clk IMX8MQ_CLK_PCIE1_AUX>, |
| <&clk IMX8MQ_CLK_PCIE1_PHY>, |
| <&pcie0_refclk>; |
| clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; |
| status = "okay"; |
| }; |
| |
| &pgc_gpu { |
| power-supply = <&buck3_reg>; |
| }; |
| |
| &qspi0 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_qspi>; |
| status = "okay"; |
| |
| mx25l51245g: flash@0 { |
| reg = <0>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "jedec,spi-nor"; |
| spi-max-frequency = <29000000>; |
| }; |
| }; |
| |
| &snvs_pwrkey { |
| status = "okay"; |
| }; |
| |
| &uart1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart1>; |
| status = "okay"; |
| }; |
| |
| &usb3_phy1 { |
| status = "okay"; |
| }; |
| |
| &usb_dwc3_1 { |
| dr_mode = "host"; |
| status = "okay"; |
| }; |
| |
| &usdhc1 { |
| assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>; |
| assigned-clock-rates = <400000000>; |
| pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
| pinctrl-0 = <&pinctrl_usdhc1>; |
| pinctrl-1 = <&pinctrl_usdhc1_100mhz>; |
| pinctrl-2 = <&pinctrl_usdhc1_200mhz>; |
| vqmmc-supply = <&buck7_reg>; |
| bus-width = <8>; |
| non-removable; |
| no-sd; |
| no-sdio; |
| status = "okay"; |
| }; |
| |
| &usdhc2 { |
| assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>; |
| assigned-clock-rates = <200000000>; |
| pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
| pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; |
| pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; |
| pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; |
| cd-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; |
| vmmc-supply = <®_usdhc2_vmmc>; |
| status = "okay"; |
| }; |
| |
| &wdog1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_wdog>; |
| fsl,ext-reset-output; |
| status = "okay"; |
| }; |
| |
| &iomuxc { |
| pinctrl_buck2: vddarmgrp { |
| fsl,pins = < |
| MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19 |
| >; |
| |
| }; |
| |
| pinctrl_fec1: fec1grp { |
| fsl,pins = < |
| MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 |
| MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 |
| MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f |
| MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f |
| MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f |
| MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f |
| MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 |
| MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 |
| MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 |
| MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 |
| MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f |
| MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 |
| MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 |
| MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f |
| MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 |
| >; |
| }; |
| |
| pinctrl_i2c1: i2c1grp { |
| fsl,pins = < |
| MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f |
| MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f |
| >; |
| }; |
| |
| pinctrl_i2c2: i2c2grp { |
| fsl,pins = < |
| MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000067 |
| MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000067 |
| >; |
| }; |
| |
| pinctrl_pcie0: pcie0grp { |
| fsl,pins = < |
| MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x76 |
| MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x16 |
| >; |
| }; |
| |
| pinctrl_pmic: pmicgrp { |
| fsl,pins = < |
| MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x80 /* PMIC intr */ |
| >; |
| }; |
| |
| pinctrl_qspi: qspigrp { |
| fsl,pins = < |
| MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82 |
| MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 |
| MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 |
| MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 |
| MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 |
| MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 |
| |
| >; |
| }; |
| |
| pinctrl_reg_usdhc2: regusdhc2gpiogrp { |
| fsl,pins = < |
| MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 |
| >; |
| }; |
| |
| pinctrl_uart1: uart1grp { |
| fsl,pins = < |
| MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 |
| MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 |
| >; |
| }; |
| |
| pinctrl_usdhc1: usdhc1grp { |
| fsl,pins = < |
| MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 |
| MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 |
| MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 |
| MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 |
| MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 |
| MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 |
| MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 |
| MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 |
| MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 |
| MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 |
| MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 |
| MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 |
| >; |
| }; |
| |
| pinctrl_usdhc1_100mhz: usdhc1-100grp { |
| fsl,pins = < |
| MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d |
| MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd |
| MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd |
| MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd |
| MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd |
| MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd |
| MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd |
| MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd |
| MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd |
| MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd |
| MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d |
| MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 |
| >; |
| }; |
| |
| pinctrl_usdhc1_200mhz: usdhc1-200grp { |
| fsl,pins = < |
| MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f |
| MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf |
| MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf |
| MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf |
| MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf |
| MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf |
| MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf |
| MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf |
| MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf |
| MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf |
| MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f |
| MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 |
| >; |
| }; |
| |
| pinctrl_usdhc2_gpio: usdhc2grpgpiogrp { |
| fsl,pins = < |
| MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 |
| >; |
| }; |
| |
| pinctrl_usdhc2: usdhc2grp { |
| fsl,pins = < |
| MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 |
| MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 |
| MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 |
| MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 |
| MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 |
| MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 |
| MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 |
| >; |
| }; |
| |
| pinctrl_usdhc2_100mhz: usdhc2-100grp { |
| fsl,pins = < |
| MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85 |
| MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5 |
| MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5 |
| MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5 |
| MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5 |
| MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5 |
| MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 |
| >; |
| }; |
| |
| pinctrl_usdhc2_200mhz: usdhc2-200grp { |
| fsl,pins = < |
| MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87 |
| MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7 |
| MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7 |
| MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7 |
| MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7 |
| MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7 |
| MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 |
| >; |
| }; |
| |
| pinctrl_wdog: wdog1grp { |
| fsl,pins = < |
| MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 |
| >; |
| }; |
| }; |