arch/arm/dts/sun50i-h5-cpu-opp.dtsi

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
// Copyright (C) 2020 Chen-Yu Tsai <wens@csie.org>

/ {
	cpu_opp_table: cpu-opp-table {
		compatible = "operating-points-v2";
		opp-shared;

		opp-408000000 {
			opp-hz = /bits/ 64 <408000000>;
			opp-microvolt = <1000000 1000000 1310000>;
			clock-latency-ns = <244144>; /* 8 32k periods */
		};

		opp-648000000 {
			opp-hz = /bits/ 64 <648000000>;
			opp-microvolt = <1040000 1040000 1310000>;
			clock-latency-ns = <244144>; /* 8 32k periods */
		};

		opp-816000000 {
			opp-hz = /bits/ 64 <816000000>;
			opp-microvolt = <1080000 1080000 1310000>;
			clock-latency-ns = <244144>; /* 8 32k periods */
		};

		opp-912000000 {
			opp-hz = /bits/ 64 <912000000>;
			opp-microvolt = <1120000 1120000 1310000>;
			clock-latency-ns = <244144>; /* 8 32k periods */
		};

		opp-960000000 {
			opp-hz = /bits/ 64 <960000000>;
			opp-microvolt = <1160000 1160000 1310000>;
			clock-latency-ns = <244144>; /* 8 32k periods */
		};

		opp-1008000000 {
			opp-hz = /bits/ 64 <1008000000>;
			opp-microvolt = <1200000 1200000 1310000>;
			clock-latency-ns = <244144>; /* 8 32k periods */
		};

		opp-1056000000 {
			opp-hz = /bits/ 64 <1056000000>;
			opp-microvolt = <1240000 1240000 1310000>;
			clock-latency-ns = <244144>; /* 8 32k periods */
		};

		opp-1104000000 {
			opp-hz = /bits/ 64 <1104000000>;
			opp-microvolt = <1260000 1260000 1310000>;
			clock-latency-ns = <244144>; /* 8 32k periods */
		};

		opp-1152000000 {
			opp-hz = /bits/ 64 <1152000000>;
			opp-microvolt = <1300000 1300000 1310000>;
			clock-latency-ns = <244144>; /* 8 32k periods */
		};
	};
};

&cpu0 {
	operating-points-v2 = <&cpu_opp_table>;
};

&cpu1 {
	operating-points-v2 = <&cpu_opp_table>;
};

&cpu2 {
	operating-points-v2 = <&cpu_opp_table>;
};

&cpu3 {
	operating-points-v2 = <&cpu_opp_table>;
};