| /* |
| * Copyright (C) 2012 Freescale Semiconductor, Inc. |
| * |
| * Author: Fabio Estevam <fabio.estevam@freescale.com> |
| * |
| * SPDX-License-Identifier: GPL-2.0+ |
| */ |
| |
| #include <asm/arch/clock.h> |
| #include <asm/arch/imx-regs.h> |
| #include <asm/arch/iomux.h> |
| #include <asm/arch/mx6-pins.h> |
| #include <asm/errno.h> |
| #include <asm/gpio.h> |
| #include <asm/imx-common/mxc_i2c.h> |
| #include <asm/imx-common/iomux-v3.h> |
| #include <asm/imx-common/boot_mode.h> |
| #include <asm/imx-common/video.h> |
| #include <mmc.h> |
| #include <fsl_esdhc.h> |
| #include <miiphy.h> |
| #include <netdev.h> |
| #include <asm/arch/mxc_hdmi.h> |
| #include <asm/arch/crm_regs.h> |
| #include <asm/io.h> |
| #include <asm/arch/sys_proto.h> |
| #include <i2c.h> |
| #include <power/pmic.h> |
| #include <power/pfuze100_pmic.h> |
| DECLARE_GLOBAL_DATA_PTR; |
| |
| #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ |
| PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ |
| PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
| |
| #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ |
| PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ |
| PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
| |
| #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ |
| PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) |
| |
| #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ |
| PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) |
| |
| #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ |
| PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ |
| PAD_CTL_ODE | PAD_CTL_SRE_FAST) |
| |
| #define I2C_PMIC 1 |
| |
| #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL) |
| |
| #define DISP0_PWR_EN IMX_GPIO_NR(1, 21) |
| |
| int dram_init(void) |
| { |
| gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); |
| |
| return 0; |
| } |
| |
| iomux_v3_cfg_t const uart1_pads[] = { |
| MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), |
| MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), |
| }; |
| |
| iomux_v3_cfg_t const enet_pads[] = { |
| MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| /* AR8031 PHY Reset */ |
| MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| }; |
| |
| static void setup_iomux_enet(void) |
| { |
| imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); |
| |
| /* Reset AR8031 PHY */ |
| gpio_direction_output(IMX_GPIO_NR(1, 25) , 0); |
| udelay(500); |
| gpio_set_value(IMX_GPIO_NR(1, 25), 1); |
| } |
| |
| iomux_v3_cfg_t const usdhc2_pads[] = { |
| MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ |
| }; |
| |
| iomux_v3_cfg_t const usdhc3_pads[] = { |
| MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ |
| }; |
| |
| iomux_v3_cfg_t const usdhc4_pads[] = { |
| MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| }; |
| |
| iomux_v3_cfg_t const ecspi1_pads[] = { |
| MX6_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), |
| MX6_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), |
| MX6_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), |
| MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| }; |
| |
| static iomux_v3_cfg_t const rgb_pads[] = { |
| MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL), |
| MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| MX6_PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| }; |
| |
| static void enable_rgb(struct display_info_t const *dev) |
| { |
| imx_iomux_v3_setup_multiple_pads(rgb_pads, ARRAY_SIZE(rgb_pads)); |
| gpio_direction_output(DISP0_PWR_EN, 1); |
| } |
| |
| static struct i2c_pads_info i2c_pad_info1 = { |
| .scl = { |
| .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD, |
| .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD, |
| .gp = IMX_GPIO_NR(4, 12) |
| }, |
| .sda = { |
| .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD, |
| .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD, |
| .gp = IMX_GPIO_NR(4, 13) |
| } |
| }; |
| |
| static void setup_spi(void) |
| { |
| imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); |
| } |
| |
| iomux_v3_cfg_t const pcie_pads[] = { |
| MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), /* POWER */ |
| MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), /* RESET */ |
| }; |
| |
| static void setup_pcie(void) |
| { |
| imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads)); |
| } |
| |
| iomux_v3_cfg_t const di0_pads[] = { |
| MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* DISP0_CLK */ |
| MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* DISP0_HSYNC */ |
| MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* DISP0_VSYNC */ |
| }; |
| |
| static void setup_iomux_uart(void) |
| { |
| imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); |
| } |
| |
| #ifdef CONFIG_FSL_ESDHC |
| struct fsl_esdhc_cfg usdhc_cfg[3] = { |
| {USDHC2_BASE_ADDR}, |
| {USDHC3_BASE_ADDR}, |
| {USDHC4_BASE_ADDR}, |
| }; |
| |
| #define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2) |
| #define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0) |
| |
| int board_mmc_getcd(struct mmc *mmc) |
| { |
| struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; |
| int ret = 0; |
| |
| switch (cfg->esdhc_base) { |
| case USDHC2_BASE_ADDR: |
| ret = !gpio_get_value(USDHC2_CD_GPIO); |
| break; |
| case USDHC3_BASE_ADDR: |
| ret = !gpio_get_value(USDHC3_CD_GPIO); |
| break; |
| case USDHC4_BASE_ADDR: |
| ret = 1; /* eMMC/uSDHC4 is always present */ |
| break; |
| } |
| |
| return ret; |
| } |
| |
| int board_mmc_init(bd_t *bis) |
| { |
| s32 status = 0; |
| int i; |
| |
| /* |
| * According to the board_mmc_init() the following map is done: |
| * (U-boot device node) (Physical Port) |
| * mmc0 SD2 |
| * mmc1 SD3 |
| * mmc2 eMMC |
| */ |
| for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { |
| switch (i) { |
| case 0: |
| imx_iomux_v3_setup_multiple_pads( |
| usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); |
| gpio_direction_input(USDHC2_CD_GPIO); |
| usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); |
| break; |
| case 1: |
| imx_iomux_v3_setup_multiple_pads( |
| usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); |
| gpio_direction_input(USDHC3_CD_GPIO); |
| usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); |
| break; |
| case 2: |
| imx_iomux_v3_setup_multiple_pads( |
| usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); |
| usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); |
| break; |
| default: |
| printf("Warning: you configured more USDHC controllers" |
| "(%d) then supported by the board (%d)\n", |
| i + 1, CONFIG_SYS_FSL_USDHC_NUM); |
| return status; |
| } |
| |
| status |= fsl_esdhc_initialize(bis, &usdhc_cfg[i]); |
| } |
| |
| return status; |
| } |
| #endif |
| |
| int mx6_rgmii_rework(struct phy_device *phydev) |
| { |
| unsigned short val; |
| |
| /* To enable AR8031 ouput a 125MHz clk from CLK_25M */ |
| phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); |
| phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); |
| phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); |
| |
| val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); |
| val &= 0xffe3; |
| val |= 0x18; |
| phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); |
| |
| /* introduce tx clock delay */ |
| phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); |
| val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); |
| val |= 0x0100; |
| phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); |
| |
| return 0; |
| } |
| |
| int board_phy_config(struct phy_device *phydev) |
| { |
| mx6_rgmii_rework(phydev); |
| |
| if (phydev->drv->config) |
| phydev->drv->config(phydev); |
| |
| return 0; |
| } |
| |
| #if defined(CONFIG_VIDEO_IPUV3) |
| static void disable_lvds(struct display_info_t const *dev) |
| { |
| struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; |
| |
| int reg = readl(&iomux->gpr[2]); |
| |
| reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK | |
| IOMUXC_GPR2_LVDS_CH1_MODE_MASK); |
| |
| writel(reg, &iomux->gpr[2]); |
| } |
| |
| static void do_enable_hdmi(struct display_info_t const *dev) |
| { |
| disable_lvds(dev); |
| imx_enable_hdmi_phy(); |
| } |
| |
| static void enable_lvds(struct display_info_t const *dev) |
| { |
| struct iomuxc *iomux = (struct iomuxc *) |
| IOMUXC_BASE_ADDR; |
| u32 reg = readl(&iomux->gpr[2]); |
| reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT | |
| IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT; |
| writel(reg, &iomux->gpr[2]); |
| } |
| |
| struct display_info_t const displays[] = {{ |
| .bus = -1, |
| .addr = 0, |
| .pixfmt = IPU_PIX_FMT_RGB666, |
| .detect = NULL, |
| .enable = enable_lvds, |
| .mode = { |
| .name = "Hannstar-XGA", |
| .refresh = 60, |
| .xres = 1024, |
| .yres = 768, |
| .pixclock = 15385, |
| .left_margin = 220, |
| .right_margin = 40, |
| .upper_margin = 21, |
| .lower_margin = 7, |
| .hsync_len = 60, |
| .vsync_len = 10, |
| .sync = FB_SYNC_EXT, |
| .vmode = FB_VMODE_NONINTERLACED |
| } }, { |
| .bus = -1, |
| .addr = 0, |
| .pixfmt = IPU_PIX_FMT_RGB24, |
| .detect = detect_hdmi, |
| .enable = do_enable_hdmi, |
| .mode = { |
| .name = "HDMI", |
| .refresh = 60, |
| .xres = 1024, |
| .yres = 768, |
| .pixclock = 15385, |
| .left_margin = 220, |
| .right_margin = 40, |
| .upper_margin = 21, |
| .lower_margin = 7, |
| .hsync_len = 60, |
| .vsync_len = 10, |
| .sync = FB_SYNC_EXT, |
| .vmode = FB_VMODE_NONINTERLACED |
| } }, { |
| .bus = 0, |
| .addr = 0, |
| .pixfmt = IPU_PIX_FMT_RGB24, |
| .detect = NULL, |
| .enable = enable_rgb, |
| .mode = { |
| .name = "SEIKO-WVGA", |
| .refresh = 60, |
| .xres = 800, |
| .yres = 480, |
| .pixclock = 29850, |
| .left_margin = 89, |
| .right_margin = 164, |
| .upper_margin = 23, |
| .lower_margin = 10, |
| .hsync_len = 10, |
| .vsync_len = 10, |
| .sync = 0, |
| .vmode = FB_VMODE_NONINTERLACED |
| } } }; |
| size_t display_count = ARRAY_SIZE(displays); |
| |
| static void setup_display(void) |
| { |
| struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
| struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; |
| int reg; |
| |
| /* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */ |
| imx_iomux_v3_setup_multiple_pads(di0_pads, ARRAY_SIZE(di0_pads)); |
| |
| enable_ipu_clock(); |
| imx_setup_hdmi(); |
| |
| /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */ |
| reg = readl(&mxc_ccm->CCGR3); |
| reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK; |
| writel(reg, &mxc_ccm->CCGR3); |
| |
| /* set LDB0, LDB1 clk select to 011/011 */ |
| reg = readl(&mxc_ccm->cs2cdr); |
| reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
| | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); |
| reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
| | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); |
| writel(reg, &mxc_ccm->cs2cdr); |
| |
| reg = readl(&mxc_ccm->cscmr2); |
| reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV; |
| writel(reg, &mxc_ccm->cscmr2); |
| |
| reg = readl(&mxc_ccm->chsccdr); |
| reg |= (CHSCCDR_CLK_SEL_LDB_DI0 |
| << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); |
| reg |= (CHSCCDR_CLK_SEL_LDB_DI0 |
| << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET); |
| writel(reg, &mxc_ccm->chsccdr); |
| |
| reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
| | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
| | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
| | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
| | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
| | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
| | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
| | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED |
| | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0; |
| writel(reg, &iomux->gpr[2]); |
| |
| reg = readl(&iomux->gpr[3]); |
| reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
| | IOMUXC_GPR3_HDMI_MUX_CTL_MASK)) |
| | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 |
| << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET); |
| writel(reg, &iomux->gpr[3]); |
| } |
| #endif /* CONFIG_VIDEO_IPUV3 */ |
| |
| /* |
| * Do not overwrite the console |
| * Use always serial for U-Boot console |
| */ |
| int overwrite_console(void) |
| { |
| return 1; |
| } |
| |
| int board_eth_init(bd_t *bis) |
| { |
| setup_iomux_enet(); |
| setup_pcie(); |
| |
| return cpu_eth_init(bis); |
| } |
| |
| int board_early_init_f(void) |
| { |
| setup_iomux_uart(); |
| #if defined(CONFIG_VIDEO_IPUV3) |
| setup_display(); |
| #endif |
| |
| return 0; |
| } |
| |
| int board_init(void) |
| { |
| /* address of boot parameters */ |
| gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; |
| |
| #ifdef CONFIG_MXC_SPI |
| setup_spi(); |
| #endif |
| setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); |
| |
| return 0; |
| } |
| |
| static int pfuze_init(void) |
| { |
| struct pmic *p; |
| int ret; |
| unsigned int reg; |
| |
| ret = power_pfuze100_init(I2C_PMIC); |
| if (ret) |
| return ret; |
| |
| p = pmic_get("PFUZE100"); |
| ret = pmic_probe(p); |
| if (ret) |
| return ret; |
| |
| pmic_reg_read(p, PFUZE100_DEVICEID, ®); |
| printf("PMIC: PFUZE100 ID=0x%02x\n", reg); |
| |
| /* Increase VGEN3 from 2.5 to 2.8V */ |
| pmic_reg_read(p, PFUZE100_VGEN3VOL, ®); |
| reg &= ~0xf; |
| reg |= 0xa; |
| pmic_reg_write(p, PFUZE100_VGEN3VOL, reg); |
| |
| /* Increase VGEN5 from 2.8 to 3V */ |
| pmic_reg_read(p, PFUZE100_VGEN5VOL, ®); |
| reg &= ~0xf; |
| reg |= 0xc; |
| pmic_reg_write(p, PFUZE100_VGEN5VOL, reg); |
| |
| /* Set SW1AB stanby volage to 0.975V */ |
| pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®); |
| reg &= ~0x3f; |
| reg |= 0x1b; |
| pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg); |
| |
| /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ |
| pmic_reg_read(p, PUZE_100_SW1ABCONF, ®); |
| reg &= ~0xc0; |
| reg |= 0x40; |
| pmic_reg_write(p, PUZE_100_SW1ABCONF, reg); |
| |
| /* Set SW1C standby voltage to 0.975V */ |
| pmic_reg_read(p, PFUZE100_SW1CSTBY, ®); |
| reg &= ~0x3f; |
| reg |= 0x1b; |
| pmic_reg_write(p, PFUZE100_SW1CSTBY, reg); |
| |
| /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */ |
| pmic_reg_read(p, PFUZE100_SW1CCONF, ®); |
| reg &= ~0xc0; |
| reg |= 0x40; |
| pmic_reg_write(p, PFUZE100_SW1CCONF, reg); |
| |
| return 0; |
| } |
| |
| #ifdef CONFIG_MXC_SPI |
| int board_spi_cs_gpio(unsigned bus, unsigned cs) |
| { |
| return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1; |
| } |
| #endif |
| |
| #ifdef CONFIG_CMD_BMODE |
| static const struct boot_mode board_boot_modes[] = { |
| /* 4 bit bus width */ |
| {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, |
| {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, |
| /* 8 bit bus width */ |
| {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)}, |
| {NULL, 0}, |
| }; |
| #endif |
| |
| int board_late_init(void) |
| { |
| #ifdef CONFIG_CMD_BMODE |
| add_board_boot_modes(board_boot_modes); |
| #endif |
| pfuze_init(); |
| |
| return 0; |
| } |
| |
| int checkboard(void) |
| { |
| puts("Board: MX6-SabreSD\n"); |
| return 0; |
| } |