| /* |
| * bur_am335x_common.h |
| * |
| * common parts used by B&R AM335x based boards |
| * |
| * Copyright (C) 2016 Hannes Schmelzer <oe5hpm@oevsv.at> - |
| * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com |
| * |
| * SPDX-License-Identifier: GPL-2.0+ |
| */ |
| |
| #ifndef __BUR_AM335X_COMMON_H__ |
| #define __BUR_AM335X_COMMON_H__ |
| /* ------------------------------------------------------------------------- */ |
| #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ |
| |
| /* Timer information */ |
| #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ |
| #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ |
| #define CONFIG_POWER_TPS65217 |
| |
| #include <asm/arch/omap.h> |
| |
| /* NS16550 Configuration */ |
| #define CONFIG_SYS_NS16550_SERIAL |
| #define CONFIG_SYS_NS16550_REG_SIZE (-4) |
| #define CONFIG_SYS_NS16550_CLK 48000000 |
| #define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ |
| |
| /* Network defines */ |
| #define CONFIG_MII /* Required in net/eth.c */ |
| #define CONFIG_PHY_NATSEMI |
| |
| /* |
| * SPL related defines. The Public RAM memory map the ROM defines the |
| * area between 0x402F0400 and 0x4030B800 as a download area and |
| * 0x4030B800 to 0x4030CE00 as a public stack area. The ROM also |
| * supports X-MODEM loading via UART, and we leverage this and then use |
| * Y-MODEM to load u-boot.img, when booted over UART. We must also include |
| * the scratch space that U-Boot uses in SRAM. |
| */ |
| #define CONFIG_SPL_TEXT_BASE 0x402F0400 |
| #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ |
| CONFIG_SPL_TEXT_BASE) |
| |
| /* |
| * Since SPL did pll and ddr initialization for us, |
| * we don't need to do it twice. |
| */ |
| #if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT) |
| #define CONFIG_SKIP_LOWLEVEL_INIT |
| #endif /* !CONFIG_SPL_BUILD, ... */ |
| /* |
| * Our DDR memory always starts at 0x80000000 and U-Boot shall have |
| * relocated itself to higher in memory by the time this value is used. |
| */ |
| #define CONFIG_SYS_LOAD_ADDR 0x80000000 |
| /* |
| * ---------------------------------------------------------------------------- |
| * DDR information. We say (for simplicity) that we have 1 bank, |
| * always, even when we have more. We always start at 0x80000000, |
| * and we place the initial stack pointer in our SRAM. |
| */ |
| #define CONFIG_NR_DRAM_BANKS 1 |
| #define CONFIG_SYS_SDRAM_BASE 0x80000000 |
| #define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ |
| GENERATED_GBL_DATA_SIZE) |
| |
| /* I2C */ |
| #define CONFIG_SYS_I2C |
| |
| /* |
| * Our platforms make use of SPL to initalize the hardware (primarily |
| * memory) enough for full U-Boot to be loaded. We also support Falcon |
| * Mode so that the Linux kernel can be booted directly from SPL |
| * instead, if desired. We make use of the general SPL framework found |
| * under common/spl/. Given our generally common memory map, we set a |
| * number of related defaults and sizes here. |
| */ |
| /* |
| * Place the image at the start of the ROM defined image space. |
| * We limit our size to the ROM-defined downloaded image area, and use the |
| * rest of the space for stack. We load U-Boot itself into memory at |
| * 0x80800000 for legacy reasons (to not conflict with older SPLs). We |
| * have our BSS be placed 1MiB after this, to allow for the default |
| * Linux kernel address of 0x80008000 to work, in the Falcon Mode case. |
| * We have the SPL malloc pool at the end of the BSS area. |
| * |
| * ---------------------------------------------------------------------------- |
| */ |
| #define CONFIG_SPL_BSS_START_ADDR 0x80A00000 |
| #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ |
| #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ |
| CONFIG_SPL_BSS_MAX_SIZE) |
| #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN |
| |
| /* General parts of the framework, required. */ |
| |
| #endif /* ! __BUR_AM335X_COMMON_H__ */ |