| // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| /* |
| * (C) Copyright 2021 Rockchip Electronics Co., Ltd |
| */ |
| |
| #include "rockchip-u-boot.dtsi" |
| |
| / { |
| aliases { |
| mmc0 = &sdhci; |
| mmc1 = &sdmmc0; |
| }; |
| |
| chosen { |
| u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc0; |
| }; |
| |
| dmc: dmc { |
| compatible = "rockchip,rk3568-dmc"; |
| bootph-all; |
| status = "okay"; |
| }; |
| |
| otp: nvmem@fe38c000 { |
| compatible = "rockchip,rk3568-otp"; |
| reg = <0x0 0xfe38c000 0x0 0x4000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| status = "okay"; |
| |
| cpu_id: id@a { |
| reg = <0x0a 0x10>; |
| }; |
| }; |
| }; |
| |
| &xin24m { |
| bootph-all; |
| status = "okay"; |
| }; |
| |
| &cru { |
| bootph-all; |
| status = "okay"; |
| }; |
| |
| &pmucru { |
| bootph-all; |
| status = "okay"; |
| }; |
| |
| &grf { |
| bootph-all; |
| status = "okay"; |
| }; |
| |
| &pmugrf { |
| bootph-all; |
| status = "okay"; |
| }; |
| |
| &sdhci { |
| bootph-pre-ram; |
| status = "okay"; |
| }; |
| |
| &sdmmc0 { |
| bootph-pre-ram; |
| status = "okay"; |
| }; |
| |
| #ifdef CONFIG_ROCKCHIP_SPI_IMAGE |
| &binman { |
| simple-bin-spi { |
| mkimage { |
| args = "-n", CONFIG_SYS_SOC, "-T", "rksd"; |
| offset = <0x8000>; |
| }; |
| }; |
| }; |
| #endif |