| // SPDX-License-Identifier: GPL-2.0+ |
| /* |
| * Copyright 2017-2018 NXP |
| */ |
| |
| /dts-v1/; |
| |
| #include "fsl-imx8qm.dtsi" |
| #include "fsl-imx8qm-mek-u-boot.dtsi" |
| |
| / { |
| model = "Freescale i.MX8QM MEK"; |
| compatible = "fsl,imx8qm-mek", "fsl,imx8qm"; |
| |
| chosen { |
| bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200"; |
| stdout-path = &lpuart0; |
| }; |
| |
| reg_usdhc2_vmmc: usdhc2_vmmc { |
| compatible = "regulator-fixed"; |
| regulator-name = "sw-3p3-sd1"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; |
| off-on-delay = <4800>; |
| enable-active-high; |
| }; |
| }; |
| |
| &iomuxc { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_hog>; |
| |
| imx8qm-mek { |
| pinctrl_hog: hoggrp { |
| fsl,pins = < |
| SC_P_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0x0600004c |
| SC_P_QSPI1A_DATA1_LSIO_GPIO4_IO25 0x0600004c |
| SC_P_SCU_GPIO0_03_LSIO_GPIO0_IO31 0x0600004c |
| >; |
| }; |
| |
| pinctrl_fec1: fec1grp { |
| fsl,pins = < |
| SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0 |
| SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 |
| SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 |
| SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000061 |
| SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000061 |
| SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000061 |
| SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000061 |
| SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000061 |
| SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000061 |
| SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000061 |
| SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000061 |
| SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000061 |
| SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000061 |
| SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000061 |
| SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000061 |
| >; |
| }; |
| |
| pinctrl_fec2: fec2grp { |
| fsl,pins = < |
| SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0 |
| SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000060 |
| SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x00000060 |
| SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x00000060 |
| SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x00000060 |
| SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x00000060 |
| SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x00000060 |
| SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x00000060 |
| SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000060 |
| SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x00000060 |
| SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x00000060 |
| SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x00000060 |
| SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x00000060 |
| >; |
| }; |
| |
| pinctrl_lpuart0: lpuart0grp { |
| fsl,pins = < |
| SC_P_UART0_RX_DMA_UART0_RX 0x06000020 |
| SC_P_UART0_TX_DMA_UART0_TX 0x06000020 |
| >; |
| }; |
| |
| pinctrl_usdhc1: usdhc1grp { |
| fsl,pins = < |
| SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 |
| SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 |
| SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 |
| SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 |
| SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 |
| SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 |
| SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 |
| SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 |
| SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 |
| SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 |
| SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 |
| SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 |
| >; |
| }; |
| |
| pinctrl_usdhc2_gpio: usdhc2grpgpio { |
| fsl,pins = < |
| SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021 |
| SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021 |
| SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000021 |
| >; |
| }; |
| |
| pinctrl_usdhc2: usdhc2grp { |
| fsl,pins = < |
| SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 |
| SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 |
| SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 |
| SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 |
| SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 |
| SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 |
| SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 |
| >; |
| }; |
| }; |
| }; |
| |
| &usdhc1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_usdhc1>; |
| bus-width = <8>; |
| non-removable; |
| status = "okay"; |
| }; |
| |
| &usdhc2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; |
| bus-width = <4>; |
| cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; |
| wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; |
| vmmc-supply = <®_usdhc2_vmmc>; |
| status = "okay"; |
| }; |
| |
| &fec1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_fec1>; |
| phy-mode = "rgmii-txid"; |
| phy-handle = <ðphy0>; |
| fsl,magic-packet; |
| fsl,rgmii_rxc_dly; |
| status = "okay"; |
| |
| mdio { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| ethphy0: ethernet-phy@0 { |
| compatible = "ethernet-phy-ieee802.3-c22"; |
| reg = <0>; |
| at803x,eee-disabled; |
| at803x,vddio-1p8v; |
| }; |
| |
| ethphy1: ethernet-phy@1 { |
| compatible = "ethernet-phy-ieee802.3-c22"; |
| reg = <1>; |
| at803x,eee-disabled; |
| at803x,vddio-1p8v; |
| status = "disabled"; |
| }; |
| }; |
| }; |
| |
| &lpuart0 { /* console */ |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_lpuart0>; |
| status = "okay"; |
| }; |
| |
| &gpio1 { |
| status = "okay"; |
| }; |