| // SPDX-License-Identifier: GPL-2.0+ |
| /* |
| * Copyright (C) 2017, STMicroelectronics - All Rights Reserved |
| * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics. |
| */ |
| |
| #include <dt-bindings/memory/stm32-sdram.h> |
| /{ |
| clocks { |
| u-boot,dm-pre-reloc; |
| }; |
| |
| aliases { |
| /* Aliases for gpios so as to use sequence */ |
| gpio0 = &gpioa; |
| gpio1 = &gpiob; |
| gpio2 = &gpioc; |
| gpio3 = &gpiod; |
| gpio4 = &gpioe; |
| gpio5 = &gpiof; |
| gpio6 = &gpiog; |
| gpio7 = &gpioh; |
| gpio8 = &gpioi; |
| gpio9 = &gpioj; |
| gpio10 = &gpiok; |
| spi0 = &qspi; |
| }; |
| |
| soc { |
| u-boot,dm-pre-reloc; |
| pin-controller { |
| u-boot,dm-pre-reloc; |
| }; |
| |
| fmc: fmc@A0000000 { |
| compatible = "st,stm32-fmc"; |
| reg = <0xA0000000 0x1000>; |
| clocks = <&rcc 0 STM32F4_AHB3_CLOCK(FMC)>; |
| st,syscfg = <&syscfg>; |
| pinctrl-0 = <&fmc_pins_d32>; |
| pinctrl-names = "default"; |
| st,mem_remap = <4>; |
| u-boot,dm-pre-reloc; |
| |
| /* |
| * Memory configuration from sdram |
| * MICRON MT48LC4M32B2B5-6A |
| */ |
| bank0: bank@0 { |
| st,sdram-control = /bits/ 8 <NO_COL_8 |
| NO_ROW_12 |
| MWIDTH_32 |
| BANKS_4 |
| CAS_3 |
| SDCLK_2 |
| RD_BURST_EN |
| RD_PIPE_DL_0>; |
| st,sdram-timing = /bits/ 8 <TMRD_2 |
| TXSR_6 |
| TRAS_4 |
| TRC_6 |
| TWR_2 |
| TRP_2 |
| TRCD_2>; |
| st,sdram-refcount = < 1292 >; |
| }; |
| }; |
| |
| qspi: quadspi@A0001000 { |
| compatible = "st,stm32-qspi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>; |
| reg-names = "qspi", "qspi_mm"; |
| interrupts = <91>; |
| spi-max-frequency = <108000000>; |
| clocks = <&rcc 0 STM32F4_AHB3_CLOCK(QSPI)>; |
| resets = <&rcc STM32F4_AHB3_RESET(QSPI)>; |
| pinctrl-0 = <&qspi_pins>; |
| }; |
| }; |
| }; |
| |
| &clk_hse { |
| u-boot,dm-pre-reloc; |
| }; |
| |
| &clk_i2s_ckin { |
| u-boot,dm-pre-reloc; |
| }; |
| |
| &clk_lse { |
| u-boot,dm-pre-reloc; |
| }; |
| |
| &gpioa { |
| compatible = "st,stm32-gpio"; |
| u-boot,dm-pre-reloc; |
| }; |
| |
| &gpiob { |
| compatible = "st,stm32-gpio"; |
| u-boot,dm-pre-reloc; |
| }; |
| |
| &gpioc { |
| compatible = "st,stm32-gpio"; |
| u-boot,dm-pre-reloc; |
| }; |
| |
| &gpiod { |
| compatible = "st,stm32-gpio"; |
| u-boot,dm-pre-reloc; |
| }; |
| |
| &gpioe { |
| compatible = "st,stm32-gpio"; |
| u-boot,dm-pre-reloc; |
| }; |
| |
| &gpiof { |
| compatible = "st,stm32-gpio"; |
| u-boot,dm-pre-reloc; |
| }; |
| |
| &gpiog { |
| compatible = "st,stm32-gpio"; |
| u-boot,dm-pre-reloc; |
| }; |
| |
| &gpioh { |
| compatible = "st,stm32-gpio"; |
| u-boot,dm-pre-reloc; |
| }; |
| |
| &gpioi { |
| compatible = "st,stm32-gpio"; |
| u-boot,dm-pre-reloc; |
| }; |
| |
| &gpioj { |
| compatible = "st,stm32-gpio"; |
| u-boot,dm-pre-reloc; |
| }; |
| |
| &gpiok { |
| compatible = "st,stm32-gpio"; |
| u-boot,dm-pre-reloc; |
| }; |
| |
| &pinctrl { |
| fmc_pins_d32: fmc_d32@0 { |
| u-boot,dm-pre-reloc; |
| pins |
| { |
| pinmux = <STM32_PINMUX('I',10, AF12)>, /* D31 */ |
| <STM32_PINMUX('I', 9, AF12)>, /* D30 */ |
| <STM32_PINMUX('I', 7, AF12)>, /* D29 */ |
| <STM32_PINMUX('I', 6, AF12)>, /* D28 */ |
| <STM32_PINMUX('I', 3, AF12)>, /* D27 */ |
| <STM32_PINMUX('I', 2, AF12)>, /* D26 */ |
| <STM32_PINMUX('I', 1, AF12)>, /* D25 */ |
| <STM32_PINMUX('I', 0, AF12)>, /* D24 */ |
| <STM32_PINMUX('H',15, AF12)>, /* D23 */ |
| <STM32_PINMUX('H',14, AF12)>, /* D22 */ |
| <STM32_PINMUX('H',13, AF12)>, /* D21 */ |
| <STM32_PINMUX('H',12, AF12)>, /* D20 */ |
| <STM32_PINMUX('H',11, AF12)>, /* D19 */ |
| <STM32_PINMUX('H',10, AF12)>, /* D18 */ |
| <STM32_PINMUX('H', 9, AF12)>, /* D17 */ |
| <STM32_PINMUX('H', 8, AF12)>, /* D16 */ |
| |
| <STM32_PINMUX('D',10, AF12)>, /* D15 */ |
| <STM32_PINMUX('D', 9, AF12)>, /* D14 */ |
| <STM32_PINMUX('D', 8, AF12)>, /* D13 */ |
| <STM32_PINMUX('E',15, AF12)>, /* D12 */ |
| <STM32_PINMUX('E',14, AF12)>, /* D11 */ |
| <STM32_PINMUX('E',13, AF12)>, /* D10 */ |
| <STM32_PINMUX('E',12, AF12)>, /* D09 */ |
| <STM32_PINMUX('E',11, AF12)>, /* D08 */ |
| <STM32_PINMUX('E',10, AF12)>, /* D07 */ |
| <STM32_PINMUX('E', 9, AF12)>, /* D06 */ |
| <STM32_PINMUX('E', 8, AF12)>, /* D05 */ |
| <STM32_PINMUX('E', 7, AF12)>, /* D04 */ |
| <STM32_PINMUX('D', 1, AF12)>, /* D03 */ |
| <STM32_PINMUX('D', 0, AF12)>, /* D02 */ |
| <STM32_PINMUX('D',15, AF12)>, /* D01 */ |
| <STM32_PINMUX('D',14, AF12)>, /* D00 */ |
| |
| <STM32_PINMUX('E', 0, AF12)>, /* NBL0 */ |
| <STM32_PINMUX('E', 1, AF12)>, /* NBL1 */ |
| <STM32_PINMUX('I', 4, AF12)>, /* NBL2 */ |
| <STM32_PINMUX('I', 5, AF12)>, /* NBL3 */ |
| |
| <STM32_PINMUX('G', 5, AF12)>, /* BA1 */ |
| <STM32_PINMUX('G', 4, AF12)>, /* BA0 */ |
| |
| <STM32_PINMUX('G', 1, AF12)>, /* A11 */ |
| <STM32_PINMUX('G', 0, AF12)>, /* A10 */ |
| <STM32_PINMUX('F',15, AF12)>, /* A09 */ |
| <STM32_PINMUX('F',14, AF12)>, /* A08 */ |
| <STM32_PINMUX('F',13, AF12)>, /* A07 */ |
| <STM32_PINMUX('F',12, AF12)>, /* A06 */ |
| <STM32_PINMUX('F', 5, AF12)>, /* A05 */ |
| <STM32_PINMUX('F', 4, AF12)>, /* A04 */ |
| <STM32_PINMUX('F', 3, AF12)>, /* A03 */ |
| <STM32_PINMUX('F', 2, AF12)>, /* A02 */ |
| <STM32_PINMUX('F', 1, AF12)>, /* A01 */ |
| <STM32_PINMUX('F', 0, AF12)>, /* A00 */ |
| |
| <STM32_PINMUX('H', 3, AF12)>, /* SDNE0 */ |
| <STM32_PINMUX('C', 0, AF12)>, /* SDNWE */ |
| <STM32_PINMUX('F',11, AF12)>, /* SDNRAS */ |
| <STM32_PINMUX('G',15, AF12)>, /* SDNCAS */ |
| <STM32_PINMUX('H', 2, AF12)>, /* SDCKE0 */ |
| <STM32_PINMUX('G', 8, AF12)>; /* SDCLK> */ |
| slew-rate = <2>; |
| u-boot,dm-pre-reloc; |
| }; |
| }; |
| |
| qspi_pins: qspi@0 { |
| pins { |
| pinmux = <STM32_PINMUX('F',10, AF9)>, /* CLK */ |
| <STM32_PINMUX('B', 6, AF10)>, /* BK1_NCS */ |
| <STM32_PINMUX('F', 8, AF10)>, /* BK1_IO0 */ |
| <STM32_PINMUX('F', 9, AF10)>, /* BK1_IO1 */ |
| <STM32_PINMUX('F', 7, AF9)>, /* BK1_IO2 */ |
| <STM32_PINMUX('F', 6, AF9)>; /* BK1_IO3 */ |
| slew-rate = <2>; |
| }; |
| }; |
| |
| usart3_pins_a: usart3@0 { |
| u-boot,dm-pre-reloc; |
| pins1 { |
| u-boot,dm-pre-reloc; |
| }; |
| pins2 { |
| u-boot,dm-pre-reloc; |
| }; |
| }; |
| }; |
| |
| &pwrcfg { |
| u-boot,dm-pre-reloc; |
| }; |
| |
| &rcc { |
| u-boot,dm-pre-reloc; |
| }; |
| |
| &syscfg { |
| u-boot,dm-pre-reloc; |
| }; |
| |
| &qspi { |
| reg = <0xA0001000 0x1000>, <0x90000000 0x1000000>; |
| flash0: n25q128a { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "jedec,spi-nor"; |
| spi-max-frequency = <108000000>; |
| spi-tx-bus-width = <4>; |
| spi-rx-bus-width = <4>; |
| reg = <0>; |
| }; |
| }; |