| // SPDX-License-Identifier: GPL-2.0 |
| /* |
| * Device Tree Source for J721E SoC Family Main Domain peripherals |
| * |
| * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/ |
| */ |
| |
| &cbass_main { |
| msmc_ram: sram@70000000 { |
| compatible = "mmio-sram"; |
| reg = <0x0 0x70000000 0x0 0x800000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x0 0x70000000 0x800000>; |
| |
| atf-sram@0 { |
| reg = <0x0 0x20000>; |
| }; |
| }; |
| |
| gic500: interrupt-controller@1800000 { |
| compatible = "arm,gic-v3"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| #interrupt-cells = <3>; |
| interrupt-controller; |
| reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ |
| <0x00 0x01900000 0x00 0x100000>; /* GICR */ |
| |
| /* vcpumntirq: virtual CPU interface maintenance interrupt */ |
| interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| |
| gic_its: gic-its@18200000 { |
| compatible = "arm,gic-v3-its"; |
| reg = <0x00 0x01820000 0x00 0x10000>; |
| socionext,synquacer-pre-its = <0x1000000 0x400000>; |
| msi-controller; |
| #msi-cells = <1>; |
| }; |
| }; |
| |
| smmu0: smmu@36600000 { |
| compatible = "arm,smmu-v3"; |
| reg = <0x0 0x36600000 0x0 0x100000>; |
| interrupt-parent = <&gic500>; |
| interrupts = <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>; |
| interrupt-names = "eventq", "gerror"; |
| #iommu-cells = <1>; |
| }; |
| |
| secure_proxy_main: mailbox@32c00000 { |
| compatible = "ti,am654-secure-proxy"; |
| #mbox-cells = <1>; |
| reg-names = "target_data", "rt", "scfg"; |
| reg = <0x00 0x32c00000 0x00 0x100000>, |
| <0x00 0x32400000 0x00 0x100000>, |
| <0x00 0x32800000 0x00 0x100000>; |
| interrupt-names = "rx_011"; |
| interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| main_pmx0: pinmux@11c000 { |
| compatible = "pinctrl-single"; |
| /* Proxy 0 addressing */ |
| reg = <0x0 0x11c000 0x0 0x2b4>; |
| #pinctrl-cells = <1>; |
| pinctrl-single,register-width = <32>; |
| pinctrl-single,function-mask = <0xffffffff>; |
| }; |
| |
| main_uart0: serial@2800000 { |
| compatible = "ti,j721e-uart", "ti,am654-uart"; |
| reg = <0x00 0x02800000 0x00 0x100>; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; |
| clock-frequency = <48000000>; |
| current-speed = <115200>; |
| power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 146 0>; |
| clock-names = "fclk"; |
| }; |
| |
| main_uart1: serial@2810000 { |
| compatible = "ti,j721e-uart", "ti,am654-uart"; |
| reg = <0x00 0x02810000 0x00 0x100>; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; |
| clock-frequency = <48000000>; |
| current-speed = <115200>; |
| power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 278 0>; |
| clock-names = "fclk"; |
| }; |
| |
| main_uart2: serial@2820000 { |
| compatible = "ti,j721e-uart", "ti,am654-uart"; |
| reg = <0x00 0x02820000 0x00 0x100>; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; |
| clock-frequency = <48000000>; |
| current-speed = <115200>; |
| power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 279 0>; |
| clock-names = "fclk"; |
| }; |
| |
| main_uart3: serial@2830000 { |
| compatible = "ti,j721e-uart", "ti,am654-uart"; |
| reg = <0x00 0x02830000 0x00 0x100>; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; |
| clock-frequency = <48000000>; |
| current-speed = <115200>; |
| power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 280 0>; |
| clock-names = "fclk"; |
| }; |
| |
| main_uart4: serial@2840000 { |
| compatible = "ti,j721e-uart", "ti,am654-uart"; |
| reg = <0x00 0x02840000 0x00 0x100>; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; |
| clock-frequency = <48000000>; |
| current-speed = <115200>; |
| power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 281 0>; |
| clock-names = "fclk"; |
| }; |
| |
| main_uart5: serial@2850000 { |
| compatible = "ti,j721e-uart", "ti,am654-uart"; |
| reg = <0x00 0x02850000 0x00 0x100>; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; |
| clock-frequency = <48000000>; |
| current-speed = <115200>; |
| power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 282 0>; |
| clock-names = "fclk"; |
| }; |
| |
| main_uart6: serial@2860000 { |
| compatible = "ti,j721e-uart", "ti,am654-uart"; |
| reg = <0x00 0x02860000 0x00 0x100>; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; |
| clock-frequency = <48000000>; |
| current-speed = <115200>; |
| power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 283 0>; |
| clock-names = "fclk"; |
| }; |
| |
| main_uart7: serial@2870000 { |
| compatible = "ti,j721e-uart", "ti,am654-uart"; |
| reg = <0x00 0x02870000 0x00 0x100>; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; |
| clock-frequency = <48000000>; |
| current-speed = <115200>; |
| power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 284 0>; |
| clock-names = "fclk"; |
| }; |
| |
| main_uart8: serial@2880000 { |
| compatible = "ti,j721e-uart", "ti,am654-uart"; |
| reg = <0x00 0x02880000 0x00 0x100>; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; |
| clock-frequency = <48000000>; |
| current-speed = <115200>; |
| power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 285 0>; |
| clock-names = "fclk"; |
| }; |
| |
| main_uart9: serial@2890000 { |
| compatible = "ti,j721e-uart", "ti,am654-uart"; |
| reg = <0x00 0x02890000 0x00 0x100>; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; |
| clock-frequency = <48000000>; |
| current-speed = <115200>; |
| power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 286 0>; |
| clock-names = "fclk"; |
| }; |
| |
| main_sdhci0: sdhci@4f80000 { |
| compatible = "ti,j721e-sdhci-8bit"; |
| reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>; |
| interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; |
| clock-names = "clk_xin", "clk_ahb"; |
| clocks = <&k3_clks 91 1>, <&k3_clks 91 0>; |
| assigned-clocks = <&k3_clks 91 1>; |
| assigned-clock-parents = <&k3_clks 91 2>; |
| bus-width = <8>; |
| ti,otap-del-sel = <0x2>; |
| ti,trm-icp = <0x8>; |
| dma-coherent; |
| }; |
| |
| main_sdhci1: sdhci@4fb0000 { |
| compatible = "ti,j721e-sdhci-4bit"; |
| reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>; |
| interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; |
| clock-names = "clk_xin", "clk_ahb"; |
| clocks = <&k3_clks 92 0>, <&k3_clks 92 5>; |
| assigned-clocks = <&k3_clks 92 0>; |
| assigned-clock-parents = <&k3_clks 92 1>; |
| ti,otap-del-sel = <0x2>; |
| ti,trm-icp = <0x8>; |
| dma-coherent; |
| }; |
| |
| main_r5fss0: r5fss@5c00000 { |
| compatible = "ti,j721e-r5fss"; |
| lockstep-mode = <0>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x5c00000 0x00 0x5c00000 0x20000>, |
| <0x5d00000 0x00 0x5d00000 0x20000>; |
| power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>; |
| |
| main_r5fss0_core0: r5f@5c00000 { |
| compatible = "ti,j721e-r5f"; |
| reg = <0x5c00000 0x00008000>, |
| <0x5c10000 0x00008000>; |
| reg-names = "atcm", "btcm"; |
| ti,sci = <&dmsc>; |
| ti,sci-dev-id = <245>; |
| ti,sci-proc-ids = <0x06 0xFF>; |
| resets = <&k3_reset 245 1>; |
| atcm-enable = <1>; |
| btcm-enable = <1>; |
| loczrama = <1>; |
| }; |
| |
| main_r5fss0_core1: r5f@5d00000 { |
| compatible = "ti,j721e-r5f"; |
| reg = <0x5d00000 0x00008000>, |
| <0x5d10000 0x00008000>; |
| reg-names = "atcm", "btcm"; |
| ti,sci = <&dmsc>; |
| ti,sci-dev-id = <246>; |
| ti,sci-proc-ids = <0x07 0xFF>; |
| resets = <&k3_reset 246 1>; |
| atcm-enable = <1>; |
| btcm-enable = <1>; |
| loczrama = <1>; |
| }; |
| }; |
| |
| main_r5fss1: r5fss@5e00000 { |
| compatible = "ti,j721e-r5fss"; |
| lockstep-mode = <1>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x5e00000 0x00 0x5e00000 0x20000>, |
| <0x5f00000 0x00 0x5f00000 0x20000>; |
| power-domains = <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>; |
| |
| main_r5fss1_core0: r5f@5e00000 { |
| compatible = "ti,j721e-r5f"; |
| reg = <0x5e00000 0x00008000>, |
| <0x5e10000 0x00008000>; |
| reg-names = "atcm", "btcm"; |
| ti,sci = <&dmsc>; |
| ti,sci-dev-id = <247>; |
| ti,sci-proc-ids = <0x08 0xFF>; |
| resets = <&k3_reset 247 1>; |
| atcm-enable = <1>; |
| btcm-enable = <1>; |
| loczrama = <1>; |
| }; |
| |
| main_r5fss1_core1: r5f@5f00000 { |
| compatible = "ti,j721e-r5f"; |
| reg = <0x5f00000 0x00008000>, |
| <0x5f10000 0x00008000>; |
| reg-names = "atcm", "btcm"; |
| ti,sci = <&dmsc>; |
| ti,sci-dev-id = <248>; |
| ti,sci-proc-ids = <0x09 0xFF>; |
| resets = <&k3_reset 248 1>; |
| atcm-enable = <1>; |
| btcm-enable = <1>; |
| loczrama = <1>; |
| }; |
| }; |
| |
| c66_0: dsp@4d80800000 { |
| compatible = "ti,j721e-c66-dsp"; |
| reg = <0x4d 0x80800000 0x00 0x00048000>, |
| <0x4d 0x80e00000 0x00 0x00008000>, |
| <0x4d 0x80f00000 0x00 0x00008000>; |
| reg-names = "l2sram", "l1pram", "l1dram"; |
| ti,sci = <&dmsc>; |
| ti,sci-dev-id = <142>; |
| ti,sci-proc-ids = <0x03 0xFF>; |
| resets = <&k3_reset 142 1>; |
| }; |
| |
| c66_1: dsp@4d81800000 { |
| compatible = "ti,j721e-c66-dsp"; |
| reg = <0x4d 0x81800000 0x00 0x00048000>, |
| <0x4d 0x81e00000 0x00 0x00008000>, |
| <0x4d 0x81f00000 0x00 0x00008000>; |
| reg-names = "l2sram", "l1pram", "l1dram"; |
| ti,sci = <&dmsc>; |
| ti,sci-dev-id = <143>; |
| ti,sci-proc-ids = <0x04 0xFF>; |
| resets = <&k3_reset 143 1>; |
| }; |
| |
| c71_0: dsp@64800000 { |
| compatible = "ti,j721e-c71-dsp"; |
| reg = <0x00 0x64800000 0x00 0x00080000>, |
| <0x00 0x64e00000 0x00 0x0000c000>; |
| reg-names = "l2sram", "l1dram"; |
| ti,sci = <&dmsc>; |
| ti,sci-dev-id = <15>; |
| ti,sci-proc-ids = <0x30 0xFF>; |
| resets = <&k3_reset 15 1>; |
| }; |
| |
| ufs_wrapper: ufs-wrapper@4e80000 { |
| compatible = "ti,j721e-ufs"; |
| reg = <0x0 0x4e80000 0x0 0x100>; |
| power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 277 1>; |
| assigned-clocks = <&k3_clks 277 1>; |
| assigned-clock-parents = <&k3_clks 277 4>; |
| ranges; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| ufs@4e84000 { |
| compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0"; |
| reg = <0x0 0x4e84000 0x0 0x10000>; |
| interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; |
| freq-table-hz = <0 0>, <0 0>; |
| clocks = <&k3_clks 277 0>, <&k3_clks 277 1>; |
| clock-names = "core_clk", "phy_clk"; |
| assigned-clocks = <&k3_clks 277 1>; |
| assigned-clock-parents = <&k3_clks 277 4>; |
| dma-coherent; |
| }; |
| }; |
| }; |