include/configs/omap3_evm.h - platform/external/u-boot - Gitiles

 /*
  * (C) Copyright 2006-2008
  * Texas Instruments.
  * Author :
  *	Manikandan Pillai <mani.pillai@ti.com>
  * Derived from Beagle Board and 3430 SDP code by
  *	Richard Woodruff <r-woodruff2@ti.com>
  *	Syed Mohammed Khasim <khasim@ti.com>
  *
  * Manikandan Pillai <mani.pillai@ti.com>
  *
  * Configuration settings for the TI OMAP3 EVM board.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */

 #ifndef __CONFIG_H
 #define __CONFIG_H
 #include <asm/sizes.h>

 /*
  * High Level Configuration Options
  */
 #define CONFIG_ARMCORTEXA8	1	/* This is an ARM V7 CPU core */
 #define CONFIG_OMAP		1	/* in a TI OMAP core */
 #define CONFIG_OMAP34XX		1	/* which is a 34XX */
 #define CONFIG_OMAP3430		1	/* which is in a 3430 */
 #define CONFIG_OMAP3_EVM	1	/* working with EVM */

 #include <asm/arch/cpu.h>	/* get chip and board defs */
 #include <asm/arch/omap3.h>

 /* Clock Defines */
 #define V_OSCK			26000000	/* Clock output from T2 */
 #define V_SCLK			(V_OSCK >> 1)

 #undef CONFIG_USE_IRQ			/* no support for IRQs */
 #define CONFIG_MISC_INIT_R

 #define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
 #define CONFIG_SETUP_MEMORY_TAGS	1
 #define CONFIG_INITRD_TAG		1
 #define CONFIG_REVISION_TAG		1

 /*
  * Size of malloc() pool
  */
 #define CONFIG_ENV_SIZE			SZ_128K	/* Total Size Environment */
 						/* Sector */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + SZ_128K)
 #define CONFIG_SYS_GBL_DATA_SIZE	128	/* bytes reserved for */
 						/* initial data */

 /*
  * Hardware drivers
  */

 /*
  * NS16550 Configuration
  */
 #define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */

 #define CONFIG_SYS_NS16550
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	(-4)
 #define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK

 /*
  * select serial console configuration
  */
 #define CONFIG_CONS_INDEX		1
 #define CONFIG_SYS_NS16550_COM1		OMAP34XX_UART1
 #define CONFIG_SERIAL1			1	/* UART1 on OMAP3 EVM */

 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_BAUDRATE			115200
 #define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
 					115200}
 #define CONFIG_MMC			1
 #define CONFIG_OMAP3_MMC		1
 #define CONFIG_DOS_PARTITION		1

 /* commands to include */
 #include <config_cmd_default.h>

 #define CONFIG_CMD_EXT2		/* EXT2 Support			*/
 #define CONFIG_CMD_FAT		/* FAT support			*/
 #define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/

 #define CONFIG_CMD_I2C		/* I2C serial bus support	*/
 #define CONFIG_CMD_MMC		/* MMC support			*/
 #define CONFIG_CMD_ONENAND	/* ONENAND support		*/
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_PING

 #undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
 #undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
 #undef CONFIG_CMD_IMI		/* iminfo			*/
 #undef CONFIG_CMD_IMLS		/* List all found images	*/

 #define CONFIG_SYS_NO_FLASH
 #define CONFIG_SYS_I2C_SPEED		100000
 #define CONFIG_SYS_I2C_SLAVE		1
 #define CONFIG_SYS_I2C_BUS		0
 #define CONFIG_SYS_I2C_BUS_SELECT	1
 #define CONFIG_DRIVER_OMAP34XX_I2C	1

 /*
  * Board NAND Info.
  */
 #define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
 							/* to access nand */
 #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
 							/* to access */
 							/* nand at CS0 */

 #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of */
 							/* NAND devices */
 #define SECTORSIZE			512

 #define NAND_ALLOW_ERASE_ALL
 #define ADDR_COLUMN			1
 #define ADDR_PAGE			2
 #define ADDR_COLUMN_PAGE		3

 #define NAND_ChipID_UNKNOWN		0x00
 #define NAND_MAX_FLOORS			1
 #define NAND_MAX_CHIPS			1
 #define NAND_NO_RB			1
 #define CONFIG_SYS_NAND_WP

 #define CONFIG_JFFS2_NAND
 /* nand device jffs2 lives on */
 #define CONFIG_JFFS2_DEV		"nand0"
 /* start of jffs2 partition */
 #define CONFIG_JFFS2_PART_OFFSET	0x680000
 #define CONFIG_JFFS2_PART_SIZE		0xf980000	/* sz of jffs2 part */

 /* Environment information */
 #define CONFIG_BOOTDELAY	10

 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"loadaddr=0x82000000\0" \
 	"console=ttyS2,115200n8\0" \
 	"mmcargs=setenv bootargs console=${console} " \
 		"root=/dev/mmcblk0p2 rw " \
 		"rootfstype=ext3 rootwait\0" \
 	"nandargs=setenv bootargs console=${console} " \
 		"root=/dev/mtdblock4 rw " \
 		"rootfstype=jffs2\0" \
 	"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
 	"bootscript=echo Running bootscript from mmc ...; " \
 		"autoscr ${loadaddr}\0" \
 	"loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
 	"mmcboot=echo Booting from mmc ...; " \
 		"run mmcargs; " \
 		"bootm ${loadaddr}\0" \
 	"nandboot=echo Booting from nand ...; " \
 		"run nandargs; " \
 		"onenand read ${loadaddr} 280000 400000; " \
 		"bootm ${loadaddr}\0" \

 #define CONFIG_BOOTCOMMAND \
 	"if mmcinit; then " \
 		"if run loadbootscript; then " \
 			"run bootscript; " \
 		"else " \
 			"if run loaduimage; then " \
 				"run mmcboot; " \
 			"else run nandboot; " \
 			"fi; " \
 		"fi; " \
 	"else run nandboot; fi"

 #define CONFIG_AUTO_COMPLETE	1
 /*
  * Miscellaneous configurable options
  */
 #define V_PROMPT		"OMAP3_EVM # "

 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
 #define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
 #define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #define CONFIG_SYS_PROMPT		V_PROMPT
 #define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
 /* Print Buffer Size */
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
 					sizeof(CONFIG_SYS_PROMPT) + 16)
 #define CONFIG_SYS_MAXARGS		16	/* max number of command */
 						/* args */
 /* Boot Argument Buffer Size */
 #define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
 /* memtest works on */
 #define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
 #define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
 					0x01F00000) /* 31MB */

 #define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0) /* default load */
 								/* address */

 /*
  * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
  * 32KHz clk, or from external sig. This rate is divided by a local divisor.
  */
 #define V_PVT				7

 #define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
 #define CONFIG_SYS_PVT			V_PVT	/* 2^(pvt+1) */
 #define CONFIG_SYS_HZ			((V_SCLK) / (2 << CONFIG_SYS_PVT))

 /*-----------------------------------------------------------------------
  * Stack sizes
  *
  * The stack sizes are set up in start.S using the settings below
  */
 #define CONFIG_STACKSIZE	SZ_128K	/* regular stack */
 #ifdef CONFIG_USE_IRQ
 #define CONFIG_STACKSIZE_IRQ	SZ_4K	/* IRQ stack */
 #define CONFIG_STACKSIZE_FIQ	SZ_4K	/* FIQ stack */
 #endif

 /*-----------------------------------------------------------------------
  * Physical Memory Map
  */
 #define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
 #define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
 #define PHYS_SDRAM_1_SIZE	SZ_32M	/* at least 32 meg */
 #define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1

 /* SDRAM Bank Allocation method */
 #define SDRC_R_B_C		1

 /*-----------------------------------------------------------------------
  * FLASH and environment organization
  */

 /* **** PISMO SUPPORT *** */

 /* Configure the PISMO */
 #define PISMO1_NAND_SIZE		GPMC_SIZE_128M
 #define PISMO1_ONEN_SIZE		GPMC_SIZE_128M

 #define CONFIG_SYS_MAX_FLASH_SECT	520	/* max number of sectors */
 						/* on one chip */
 #define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of flash banks */
 #define CONFIG_SYS_MONITOR_LEN		SZ_256K	/* Reserve 2 sectors */

 #define CONFIG_SYS_FLASH_BASE		boot_flash_base

 /* Monitor at start of flash */
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP

 #define CONFIG_ENV_IS_IN_ONENAND	1
 #define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
 #define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */

 #define CONFIG_SYS_ENV_SECT_SIZE	boot_flash_sec
 #define CONFIG_ENV_OFFSET		boot_flash_off
 #define CONFIG_ENV_ADDR			boot_flash_env_addr

 /*-----------------------------------------------------------------------
  * CFI FLASH driver setup
  */
 /* timeout values are in ticks */
 #define CONFIG_SYS_FLASH_ERASE_TOUT	(100 * CONFIG_SYS_HZ)
 #define CONFIG_SYS_FLASH_WRITE_TOUT	(100 * CONFIG_SYS_HZ)

 /* Flash banks JFFS2 should use */
 #define CONFIG_SYS_MAX_MTD_BANKS	(CONFIG_SYS_MAX_FLASH_BANKS + \
 					CONFIG_SYS_MAX_NAND_DEVICE)
 #define CONFIG_SYS_JFFS2_MEM_NAND
 /* use flash_info[2] */
 #define CONFIG_SYS_JFFS2_FIRST_BANK	CONFIG_SYS_MAX_FLASH_BANKS
 #define CONFIG_SYS_JFFS2_NUM_BANKS	1

 #ifndef __ASSEMBLY__
 extern gpmc_csx_t *nand_cs_base;
 extern gpmc_t *gpmc_cfg_base;
 extern unsigned int boot_flash_base;
 extern volatile unsigned int boot_flash_env_addr;
 extern unsigned int boot_flash_off;
 extern unsigned int boot_flash_sec;
 extern unsigned int boot_flash_type;
 #endif


 #define WRITE_NAND_COMMAND(d, adr)\
 			writel(d, &nand_cs_base->nand_cmd)
 #define WRITE_NAND_ADDRESS(d, adr)\
 			writel(d, &nand_cs_base->nand_adr)
 #define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat)
 #define READ_NAND(adr) readl(&nand_cs_base->nand_dat)

 /* Other NAND Access APIs */
 #define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \
 			while (0)
 #define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \
 			while (0)
 #define NAND_DISABLE_CE(nand)
 #define NAND_ENABLE_CE(nand)
 #define NAND_WAIT_READY(nand)	udelay(10)

 /*----------------------------------------------------------------------------
  * SMSC9115 Ethernet from SMSC9118 family
  *----------------------------------------------------------------------------
  */
 #if defined(CONFIG_CMD_NET)

 #define CONFIG_DRIVER_SMC911X
 #define CONFIG_DRIVER_SMC911X_32_BIT
 #define CONFIG_DRIVER_SMC911X_BASE	0x2C000000

 #endif /* (CONFIG_CMD_NET) */

 /*
  * BOOTP fields
  */

 #define CONFIG_BOOTP_SUBNETMASK		0x00000001
 #define CONFIG_BOOTP_GATEWAY		0x00000002
 #define CONFIG_BOOTP_HOSTNAME		0x00000004
 #define CONFIG_BOOTP_BOOTPATH		0x00000010

 #endif /* __CONFIG_H */
	/*
	* (C) Copyright 2006-2008
	* Texas Instruments.
	* Author :
	* Manikandan Pillai <mani.pillai@ti.com>
	* Derived from Beagle Board and 3430 SDP code by
	* Richard Woodruff <r-woodruff2@ti.com>
	* Syed Mohammed Khasim <khasim@ti.com>
	*
	* Manikandan Pillai <mani.pillai@ti.com>
	*
	* Configuration settings for the TI OMAP3 EVM board.
	*
	* See file CREDITS for list of people who contributed to this
	* project.
	*
	* This program is free software; you can redistribute it and/or
	* modify it under the terms of the GNU General Public License as
	* published by the Free Software Foundation; either version 2 of
	* the License, or (at your option) any later version.
	*
	* This program is distributed in the hope that it will be useful,
	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	* GNU General Public License for more details.
	*
	* You should have received a copy of the GNU General Public License
	* along with this program; if not, write to the Free Software
	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	* MA 02111-1307 USA
	*/

	#ifndef __CONFIG_H
	#define __CONFIG_H
	#include <asm/sizes.h>

	/*
	* High Level Configuration Options
	*/
	#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
	#define CONFIG_OMAP 1 /* in a TI OMAP core */
	#define CONFIG_OMAP34XX 1 /* which is a 34XX */
	#define CONFIG_OMAP3430 1 /* which is in a 3430 */
	#define CONFIG_OMAP3_EVM 1 /* working with EVM */

	#include <asm/arch/cpu.h> /* get chip and board defs */
	#include <asm/arch/omap3.h>

	/* Clock Defines */
	#define V_OSCK 26000000 /* Clock output from T2 */
	#define V_SCLK (V_OSCK >> 1)

	#undef CONFIG_USE_IRQ /* no support for IRQs */
	#define CONFIG_MISC_INIT_R

	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
	#define CONFIG_SETUP_MEMORY_TAGS 1
	#define CONFIG_INITRD_TAG 1
	#define CONFIG_REVISION_TAG 1

	/*
	* Size of malloc() pool
	*/
	#define CONFIG_ENV_SIZE SZ_128K /* Total Size Environment */
	/* Sector */
	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K)
	#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */
	/* initial data */

	/*
	* Hardware drivers
	*/

	/*
	* NS16550 Configuration
	*/
	#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */

	#define CONFIG_SYS_NS16550
	#define CONFIG_SYS_NS16550_SERIAL
	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK

	/*
	* select serial console configuration
	*/
	#define CONFIG_CONS_INDEX 1
	#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
	#define CONFIG_SERIAL1 1 /* UART1 on OMAP3 EVM */

	/* allow to overwrite serial and ethaddr */
	#define CONFIG_ENV_OVERWRITE
	#define CONFIG_BAUDRATE 115200
	#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
	115200}
	#define CONFIG_MMC 1
	#define CONFIG_OMAP3_MMC 1
	#define CONFIG_DOS_PARTITION 1

	/* commands to include */
	#include <config_cmd_default.h>

	#define CONFIG_CMD_EXT2 /* EXT2 Support */
	#define CONFIG_CMD_FAT /* FAT support */
	#define CONFIG_CMD_JFFS2 /* JFFS2 Support */

	#define CONFIG_CMD_I2C /* I2C serial bus support */
	#define CONFIG_CMD_MMC /* MMC support */
	#define CONFIG_CMD_ONENAND /* ONENAND support */
	#define CONFIG_CMD_DHCP
	#define CONFIG_CMD_PING

	#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
	#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
	#undef CONFIG_CMD_IMI /* iminfo */
	#undef CONFIG_CMD_IMLS /* List all found images */

	#define CONFIG_SYS_NO_FLASH
	#define CONFIG_SYS_I2C_SPEED 100000
	#define CONFIG_SYS_I2C_SLAVE 1
	#define CONFIG_SYS_I2C_BUS 0
	#define CONFIG_SYS_I2C_BUS_SELECT 1
	#define CONFIG_DRIVER_OMAP34XX_I2C 1

	/*
	* Board NAND Info.
	*/
	#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
	/* to access nand */
	#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
	/* to access */
	/* nand at CS0 */

	#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
	/* NAND devices */
	#define SECTORSIZE 512

	#define NAND_ALLOW_ERASE_ALL
	#define ADDR_COLUMN 1
	#define ADDR_PAGE 2
	#define ADDR_COLUMN_PAGE 3

	#define NAND_ChipID_UNKNOWN 0x00
	#define NAND_MAX_FLOORS 1
	#define NAND_MAX_CHIPS 1
	#define NAND_NO_RB 1
	#define CONFIG_SYS_NAND_WP

	#define CONFIG_JFFS2_NAND
	/* nand device jffs2 lives on */
	#define CONFIG_JFFS2_DEV "nand0"
	/* start of jffs2 partition */
	#define CONFIG_JFFS2_PART_OFFSET 0x680000
	#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */

	/* Environment information */
	#define CONFIG_BOOTDELAY 10

	#define CONFIG_EXTRA_ENV_SETTINGS \
	"loadaddr=0x82000000\0" \
	"console=ttyS2,115200n8\0" \
	"mmcargs=setenv bootargs console=${console} " \
	"root=/dev/mmcblk0p2 rw " \
	"rootfstype=ext3 rootwait\0" \
	"nandargs=setenv bootargs console=${console} " \
	"root=/dev/mtdblock4 rw " \
	"rootfstype=jffs2\0" \
	"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
	"bootscript=echo Running bootscript from mmc ...; " \
	"autoscr ${loadaddr}\0" \
	"loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
	"mmcboot=echo Booting from mmc ...; " \
	"run mmcargs; " \
	"bootm ${loadaddr}\0" \
	"nandboot=echo Booting from nand ...; " \
	"run nandargs; " \
	"onenand read ${loadaddr} 280000 400000; " \
	"bootm ${loadaddr}\0" \

	#define CONFIG_BOOTCOMMAND \
	"if mmcinit; then " \
	"if run loadbootscript; then " \
	"run bootscript; " \
	"else " \
	"if run loaduimage; then " \
	"run mmcboot; " \
	"else run nandboot; " \
	"fi; " \
	"fi; " \
	"else run nandboot; fi"

	#define CONFIG_AUTO_COMPLETE 1
	/*
	* Miscellaneous configurable options
	*/
	#define V_PROMPT "OMAP3_EVM # "

	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
	#define CONFIG_SYS_PROMPT V_PROMPT
	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	/* Print Buffer Size */
	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	sizeof(CONFIG_SYS_PROMPT) + 16)
	#define CONFIG_SYS_MAXARGS 16 /* max number of command */
	/* args */
	/* Boot Argument Buffer Size */
	#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
	/* memtest works on */
	#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
	#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
	0x01F00000) /* 31MB */

	#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
	/* address */

	/*
	* 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
	* 32KHz clk, or from external sig. This rate is divided by a local divisor.
	*/
	#define V_PVT 7

	#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
	#define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */
	#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PVT))

	/*-----------------------------------------------------------------------
	* Stack sizes
	*
	* The stack sizes are set up in start.S using the settings below
	*/
	#define CONFIG_STACKSIZE SZ_128K /* regular stack */
	#ifdef CONFIG_USE_IRQ
	#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */
	#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */
	#endif

	/*-----------------------------------------------------------------------
	* Physical Memory Map
	*/
	#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
	#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
	#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */
	#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1

	/* SDRAM Bank Allocation method */
	#define SDRC_R_B_C 1

	/*-----------------------------------------------------------------------
	* FLASH and environment organization
	*/

	/* ** PISMO SUPPORT * */

	/* Configure the PISMO */
	#define PISMO1_NAND_SIZE GPMC_SIZE_128M
	#define PISMO1_ONEN_SIZE GPMC_SIZE_128M

	#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */
	/* on one chip */
	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
	#define CONFIG_SYS_MONITOR_LEN SZ_256K /* Reserve 2 sectors */

	#define CONFIG_SYS_FLASH_BASE boot_flash_base

	/* Monitor at start of flash */
	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP

	#define CONFIG_ENV_IS_IN_ONENAND 1
	#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
	#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */

	#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec
	#define CONFIG_ENV_OFFSET boot_flash_off
	#define CONFIG_ENV_ADDR boot_flash_env_addr

	/*-----------------------------------------------------------------------
	* CFI FLASH driver setup
	*/
	/* timeout values are in ticks */
	#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
	#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)

	/* Flash banks JFFS2 should use */
	#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
	CONFIG_SYS_MAX_NAND_DEVICE)
	#define CONFIG_SYS_JFFS2_MEM_NAND
	/* use flash_info[2] */
	#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
	#define CONFIG_SYS_JFFS2_NUM_BANKS 1

	#ifndef __ASSEMBLY__
	extern gpmc_csx_t *nand_cs_base;
	extern gpmc_t *gpmc_cfg_base;
	extern unsigned int boot_flash_base;
	extern volatile unsigned int boot_flash_env_addr;
	extern unsigned int boot_flash_off;
	extern unsigned int boot_flash_sec;
	extern unsigned int boot_flash_type;
	#endif


	#define WRITE_NAND_COMMAND(d, adr)\
	writel(d, &nand_cs_base->nand_cmd)
	#define WRITE_NAND_ADDRESS(d, adr)\
	writel(d, &nand_cs_base->nand_adr)
	#define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat)
	#define READ_NAND(adr) readl(&nand_cs_base->nand_dat)

	/* Other NAND Access APIs */
	#define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) \|= GPMC_CONFIG_WP; } \
	while (0)
	#define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \
	while (0)
	#define NAND_DISABLE_CE(nand)
	#define NAND_ENABLE_CE(nand)
	#define NAND_WAIT_READY(nand) udelay(10)

	/*----------------------------------------------------------------------------
	* SMSC9115 Ethernet from SMSC9118 family
	*----------------------------------------------------------------------------
	*/
	#if defined(CONFIG_CMD_NET)

	#define CONFIG_DRIVER_SMC911X
	#define CONFIG_DRIVER_SMC911X_32_BIT
	#define CONFIG_DRIVER_SMC911X_BASE 0x2C000000

	#endif /* (CONFIG_CMD_NET) */

	/*
	* BOOTP fields
	*/

	#define CONFIG_BOOTP_SUBNETMASK 0x00000001
	#define CONFIG_BOOTP_GATEWAY 0x00000002
	#define CONFIG_BOOTP_HOSTNAME 0x00000004
	#define CONFIG_BOOTP_BOOTPATH 0x00000010

	#endif /* __CONFIG_H */