| /* SPDX-License-Identifier: BSD-3-Clause */ |
| /* |
| * Cadence DDR Driver |
| * |
| * Copyright (C) 2012-2021 Cadence Design Systems, Inc. |
| * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ |
| */ |
| |
| #ifndef LPDDR4_32BIT_H |
| #define LPDDR4_32BIT_H |
| |
| #define DSLICE_NUM (4U) |
| #define ASLICE_NUM (1U) |
| |
| #ifdef __cplusplus |
| extern "C" { |
| #endif |
| |
| #define DSLICE0_REG_COUNT (140U) |
| #define DSLICE1_REG_COUNT (140U) |
| #define DSLICE2_REG_COUNT (140U) |
| #define DSLICE3_REG_COUNT (140U) |
| #define ASLICE0_REG_COUNT (52U) |
| #define PHY_CORE_REG_COUNT (140U) |
| |
| #ifdef __cplusplus |
| } |
| #endif |
| |
| #endif /* LPDDR4_32BIT_H */ |