| // SPDX-License-Identifier: GPL-2.0 |
| /* |
| * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ |
| */ |
| |
| #include "k3-am64x-binman.dtsi" |
| |
| / { |
| chosen { |
| stdout-path = "serial2:115200n8"; |
| tick-timer = &timer1; |
| }; |
| |
| memory@80000000 { |
| bootph-pre-ram; |
| }; |
| }; |
| |
| &cbass_main{ |
| bootph-pre-ram; |
| timer1: timer@2400000 { |
| compatible = "ti,omap5430-timer"; |
| reg = <0x0 0x2400000 0x0 0x80>; |
| ti,timer-alwon; |
| clock-frequency = <200000000>; |
| bootph-pre-ram; |
| }; |
| }; |
| |
| &main_conf { |
| bootph-pre-ram; |
| chipid@14 { |
| bootph-pre-ram; |
| }; |
| }; |
| |
| &main_pmx0 { |
| bootph-pre-ram; |
| main_i2c0_pins_default: main-i2c0-pins-default { |
| bootph-pre-ram; |
| pinctrl-single,pins = < |
| AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */ |
| AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */ |
| >; |
| }; |
| }; |
| |
| &main_i2c0 { |
| status = "okay"; |
| bootph-pre-ram; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&main_i2c0_pins_default>; |
| clock-frequency = <400000>; |
| }; |
| |
| &main_uart0 { |
| bootph-pre-ram; |
| }; |
| |
| &usb0 { |
| dr_mode="peripheral"; |
| bootph-pre-ram; |
| }; |
| |
| &usbss0 { |
| bootph-pre-ram; |
| }; |
| |
| &main_mmc1_pins_default { |
| bootph-pre-ram; |
| }; |
| |
| &main_usb0_pins_default { |
| bootph-pre-ram; |
| }; |
| |
| &dmss { |
| bootph-pre-ram; |
| }; |
| |
| &secure_proxy_main { |
| bootph-pre-ram; |
| }; |
| |
| &dmsc { |
| bootph-pre-ram; |
| k3_sysreset: sysreset-controller { |
| compatible = "ti,sci-sysreset"; |
| bootph-pre-ram; |
| }; |
| }; |
| |
| &k3_pds { |
| bootph-pre-ram; |
| }; |
| |
| &k3_clks { |
| bootph-pre-ram; |
| }; |
| |
| &k3_reset { |
| bootph-pre-ram; |
| }; |
| |
| &sdhci0 { |
| bootph-pre-ram; |
| }; |
| |
| &sdhci1 { |
| bootph-pre-ram; |
| }; |
| |
| &cpsw3g { |
| reg = <0x0 0x8000000 0x0 0x200000>, |
| <0x0 0x43000200 0x0 0x8>; |
| reg-names = "cpsw_nuss", "mac_efuse"; |
| /delete-property/ ranges; |
| pinctrl-0 = <&mdio1_pins_default /* HACK: as MDIO driver is not DM enabled */ |
| &rgmii1_pins_default |
| &rgmii2_pins_default>; |
| |
| cpsw-phy-sel@04044 { |
| compatible = "ti,am64-phy-gmii-sel"; |
| reg = <0x0 0x43004044 0x0 0x8>; |
| }; |
| }; |
| |
| &cpsw_port2 { |
| status = "disabled"; |
| }; |