| // SPDX-License-Identifier: GPL-2.0-or-later |
| /* |
| * Copyright 2018-2019, 2021 NXP |
| * |
| */ |
| |
| #include <common.h> |
| #include <command.h> |
| #include <cpu_func.h> |
| #include <hang.h> |
| #include <image.h> |
| #include <init.h> |
| #include <log.h> |
| #include <spl.h> |
| #include <asm/global_data.h> |
| #include <asm/io.h> |
| #include <asm/mach-imx/iomux-v3.h> |
| #include <asm/arch/clock.h> |
| #include <asm/arch/imx8mn_pins.h> |
| #include <asm/arch/sys_proto.h> |
| #include <asm/mach-imx/boot_mode.h> |
| #include <asm/arch/ddr.h> |
| #include <asm/sections.h> |
| |
| #include <dm/uclass.h> |
| #include <dm/device.h> |
| #include <dm/uclass-internal.h> |
| #include <dm/device-internal.h> |
| #include <power/pmic.h> |
| #include <power/pca9450.h> |
| #include <asm/mach-imx/gpio.h> |
| #include <asm/mach-imx/mxc_i2c.h> |
| #include <fsl_esdhc_imx.h> |
| #include <mmc.h> |
| |
| DECLARE_GLOBAL_DATA_PTR; |
| |
| int spl_board_boot_device(enum boot_device boot_dev_spl) |
| { |
| return BOOT_DEVICE_BOOTROM; |
| } |
| |
| void spl_dram_init(void) |
| { |
| ddr_init(&dram_timing); |
| } |
| |
| void spl_board_init(void) |
| { |
| struct udevice *dev; |
| int ret; |
| |
| arch_misc_init(); |
| |
| puts("Normal Boot\n"); |
| |
| ret = uclass_get_device_by_name(UCLASS_CLK, |
| "clock-controller@30380000", |
| &dev); |
| if (ret < 0) |
| printf("Failed to find clock node. Check device tree\n"); |
| } |
| |
| #if CONFIG_IS_ENABLED(DM_PMIC_PCA9450) |
| int power_init_board(void) |
| { |
| struct udevice *dev; |
| int ret; |
| |
| ret = pmic_get("pmic@25", &dev); |
| if (ret == -ENODEV) { |
| puts("No pca9450@25\n"); |
| return 0; |
| } |
| if (ret != 0) |
| return ret; |
| |
| /* BUCKxOUT_DVS0/1 control BUCK123 output */ |
| pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); |
| |
| #ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE |
| /* Set VDD_SOC/VDD_DRAM to 0.8v for low drive mode */ |
| pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x10); |
| #else |
| /* increase VDD_SOC/VDD_DRAM to typical value 0.95V before first DRAM access */ |
| pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C); |
| #endif |
| /* Set DVS1 to 0.85v for suspend */ |
| /* Enable DVS control through PMIC_STBY_REQ and set B1_ENMODE=1 (ON by PMIC_ON_REQ=H) */ |
| pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14); |
| pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); |
| |
| /* set VDD_SNVS_0V8 from default 0.85V */ |
| pmic_reg_write(dev, PCA9450_LDO2CTRL, 0xC0); |
| |
| /* enable LDO4 to 1.2v */ |
| pmic_reg_write(dev, PCA9450_LDO4CTRL, 0x44); |
| |
| return 0; |
| } |
| #endif |
| |
| #ifdef CONFIG_SPL_LOAD_FIT |
| int board_fit_config_name_match(const char *name) |
| { |
| /* Just empty function now - can't decide what to choose */ |
| debug("%s: %s\n", __func__, name); |
| |
| return 0; |
| } |
| #endif |
| |
| void board_init_f(ulong dummy) |
| { |
| int ret; |
| |
| arch_cpu_init(); |
| |
| init_uart_clk(1); |
| |
| timer_init(); |
| |
| /* Clear the BSS. */ |
| memset(__bss_start, 0, __bss_end - __bss_start); |
| |
| ret = spl_init(); |
| if (ret) { |
| debug("spl_init() failed: %d\n", ret); |
| hang(); |
| } |
| |
| preloader_console_init(); |
| |
| enable_tzc380(); |
| |
| /* DDR initialization */ |
| spl_dram_init(); |
| |
| board_init_r(NULL, 0); |
| } |