arch/arm/dts/dra72-evm-common.dtsi - platform/external/u-boot - Gitiles

 /*
  * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
 /dts-v1/;

 #include "dra72x.dtsi"
 #include <dt-bindings/gpio/gpio.h>

 / {
 	compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";

 	chosen {
 		stdout-path = &uart1;
 		tick-timer = &timer2;
 	};

 	aliases {
 		display0 = &hdmi0;
 	};

 	evm_3v3: fixedregulator-evm_3v3 {
 		compatible = "regulator-fixed";
 		regulator-name = "evm_3v3";
 		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
 	};

 	extcon_usb1: extcon_usb1 {
 		compatible = "linux,extcon-usb-gpio";
 		id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
 	};

 	extcon_usb2: extcon_usb2 {
 		compatible = "linux,extcon-usb-gpio";
 		id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
 	};

 	hdmi0: connector {
 		compatible = "hdmi-connector";
 		label = "hdmi";

 		type = "a";

 		port {
 			hdmi_connector_in: endpoint {
 				remote-endpoint = <&tpd12s015_out>;
 			};
 		};
 	};

 	tpd12s015: encoder {
 		compatible = "ti,tpd12s015";

 		gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>,	/* P4, CT CP HPD */
 			<&pcf_hdmi 5 GPIO_ACTIVE_HIGH>,	/* P5, LS OE */
 			<&gpio7 12 GPIO_ACTIVE_HIGH>;	/* gpio7_12/sp1_cs2, HPD */

 		ports {
 			#address-cells = <1>;
 			#size-cells = <0>;

 			port@0 {
 				reg = <0>;

 				tpd12s015_in: endpoint {
 					remote-endpoint = <&hdmi_out>;
 				};
 			};

 			port@1 {
 				reg = <1>;

 				tpd12s015_out: endpoint {
 					remote-endpoint = <&hdmi_connector_in>;
 				};
 			};
 		};
 	};
 };

 &dra7_pmx_core {
 	mmc1_pins_default: mmc1_pins_default {
 		pinctrl-single,pins = <
 			0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
 			0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
 			0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
 			0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
 			0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
 			0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
 		>;
 	};

 	mmc2_pins_default: mmc2_pins_default {
 		pinctrl-single,pins = <
 			0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
 			0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
 			0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
 			0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
 			0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
 			0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
 			0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
 			0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
 			0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
 			0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
 		>;
 	};

 	dcan1_pins_default: dcan1_pins_default {
 		pinctrl-single,pins = <
 			0x3d0   (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
 			0x418   (PULL_UP | MUX_MODE1)	/* wakeup0.dcan1_rx */
 		>;
 	};

 	dcan1_pins_sleep: dcan1_pins_sleep {
 		pinctrl-single,pins = <
 			0x3d0   (MUX_MODE15 | PULL_UP)	/* dcan1_tx.off */
 			0x418   (MUX_MODE15 | PULL_UP)	/* wakeup0.off */
 		>;
 	};
 };

 &i2c1 {
 	status = "okay";
 	clock-frequency = <400000>;

 	tps65917: tps65917@58 {
 		compatible = "ti,tps65917";
 		reg = <0x58>;

 		interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>;  /* IRQ_SYS_1N */
 		interrupt-controller;
 		#interrupt-cells = <2>;

 		ti,system-power-controller;

 		tps65917_pmic {
 			compatible = "ti,tps65917-pmic";

 			tps65917_regulators: regulators {
 				smps1_reg: smps1 {
 					/* VDD_MPU */
 					regulator-name = "smps1";
 					regulator-min-microvolt = <850000>;
 					regulator-max-microvolt = <1250000>;
 					regulator-always-on;
 					regulator-boot-on;
 				};

 				smps2_reg: smps2 {
 					/* VDD_CORE */
 					regulator-name = "smps2";
 					regulator-min-microvolt = <850000>;
 					regulator-max-microvolt = <1060000>;
 					regulator-boot-on;
 					regulator-always-on;
 				};

 				smps3_reg: smps3 {
 					/* VDD_GPU IVA DSPEVE */
 					regulator-name = "smps3";
 					regulator-min-microvolt = <850000>;
 					regulator-max-microvolt = <1250000>;
 					regulator-boot-on;
 					regulator-always-on;
 				};

 				smps4_reg: smps4 {
 					/* VDDS1V8 */
 					regulator-name = "smps4";
 					regulator-min-microvolt = <1800000>;
 					regulator-max-microvolt = <1800000>;
 					regulator-always-on;
 					regulator-boot-on;
 				};

 				smps5_reg: smps5 {
 					/* VDD_DDR */
 					regulator-name = "smps5";
 					regulator-min-microvolt = <1350000>;
 					regulator-max-microvolt = <1350000>;
 					regulator-boot-on;
 					regulator-always-on;
 				};

 				ldo1_reg: ldo1 {
 					/* LDO1_OUT --> SDIO  */
 					regulator-name = "ldo1";
 					regulator-min-microvolt = <1800000>;
 					regulator-max-microvolt = <3300000>;
 					regulator-always-on;
 					regulator-boot-on;
 					regulator-allow-bypass;
 				};

 				ldo3_reg: ldo3 {
 					/* VDDA_1V8_PHY */
 					regulator-name = "ldo3";
 					regulator-min-microvolt = <1800000>;
 					regulator-max-microvolt = <1800000>;
 					regulator-boot-on;
 					regulator-always-on;
 				};

 				ldo5_reg: ldo5 {
 					/* VDDA_1V8_PLL */
 					regulator-name = "ldo5";
 					regulator-min-microvolt = <1800000>;
 					regulator-max-microvolt = <1800000>;
 					regulator-always-on;
 					regulator-boot-on;
 				};

 				ldo4_reg: ldo4 {
 					/* VDDA_3V_USB: VDDA_USBHS33 */
 					regulator-name = "ldo4";
 					regulator-min-microvolt = <3300000>;
 					regulator-max-microvolt = <3300000>;
 					regulator-boot-on;
 				};
 			};
 		};

 		tps65917_power_button {
 			compatible = "ti,palmas-pwrbutton";
 			interrupt-parent = <&tps65917>;
 			interrupts = <1 IRQ_TYPE_NONE>;
 			wakeup-source;
 			ti,palmas-long-press-seconds = <6>;
 		};
 	};

 	pcf_gpio_21: gpio@21 {
 		compatible = "ti,pcf8575";
 		u-boot,i2c-offset-len = <0>;
 		reg = <0x21>;
 		lines-initial-states = <0x1408>;
 		gpio-controller;
 		#gpio-cells = <2>;

 		interrupt-controller;
 		#interrupt-cells = <2>;
 	};
 };

 &i2c5 {
 	status = "okay";
 	clock-frequency = <400000>;

 	pcf_hdmi: pcf8575@26 {
 		compatible = "nxp,pcf8575";
 		u-boot,i2c-offset-len = <0>;
 		reg = <0x26>;
 		gpio-controller;
 		#gpio-cells = <2>;
 		/*
 		 * initial state is used here to keep the mdio interface
 		 * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and
 		 * VIN2_S0 driven high otherwise Ethernet stops working
 		 * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6
 		 */
 		lines-initial-states = <0x0f2b>;

 		p1 {
 			/* vin6_sel_s0: high: VIN6, low: audio */
 			gpio-hog;
 			gpios = <1 GPIO_ACTIVE_HIGH>;
 			output-low;
 			line-name = "vin6_sel_s0";
 		};
 	};
 };

 &uart1 {
 	status = "okay";
 	interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
 			      <&dra7_pmx_core 0x3e0>;
 };

 &elm {
 	status = "okay";
 };

 &gpmc {
 	/*
 	 * For the existing IOdelay configuration via U-Boot we don't
 	 * support NAND on dra72-evm. Keep it disabled. Enabling it
 	 * requires a different configuration by U-Boot.
 	 */
 	status = "disabled";
 	ranges = <0 0 0x08000000 0x01000000>;	/* minimum GPMC partition = 16MB */
 	nand@0,0 {
 		/* To use NAND, DIP switch SW5 must be set like so:
 		 * SW5.1 (NAND_SELn) = ON (LOW)
 		 * SW5.9 (GPMC_WPN) = OFF (HIGH)
 		 */
 		compatible = "ti,omap2-nand";
 		reg = <0 0 4>;          /* device IO registers */
 		interrupt-parent = <&gpmc>;
 		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
 			     <1 IRQ_TYPE_NONE>; /* termcount */
 		rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */	/* device IO registers */
 		ti,nand-ecc-opt = "bch8";
 		ti,elm-id = <&elm>;
 		nand-bus-width = <16>;
 		gpmc,device-width = <2>;
 		gpmc,sync-clk-ps = <0>;
 		gpmc,cs-on-ns = <0>;
 		gpmc,cs-rd-off-ns = <80>;
 		gpmc,cs-wr-off-ns = <80>;
 		gpmc,adv-on-ns = <0>;
 		gpmc,adv-rd-off-ns = <60>;
 		gpmc,adv-wr-off-ns = <60>;
 		gpmc,we-on-ns = <10>;
 		gpmc,we-off-ns = <50>;
 		gpmc,oe-on-ns = <4>;
 		gpmc,oe-off-ns = <40>;
 		gpmc,access-ns = <40>;
 		gpmc,wr-access-ns = <80>;
 		gpmc,rd-cycle-ns = <80>;
 		gpmc,wr-cycle-ns = <80>;
 		gpmc,bus-turnaround-ns = <0>;
 		gpmc,cycle2cycle-delay-ns = <0>;
 		gpmc,clk-activation-ns = <0>;
 		gpmc,wait-monitoring-ns = <0>;
 		gpmc,wr-data-mux-bus-ns = <0>;
 		/* MTD partition table */
 		/* All SPL-* partitions are sized to minimal length
 		 * which can be independently programmable. For
 		 * NAND flash this is equal to size of erase-block */
 		#address-cells = <1>;
 		#size-cells = <1>;
 		partition@0 {
 			label = "NAND.SPL";
 			reg = <0x00000000 0x000020000>;
 		};
 		partition@1 {
 			label = "NAND.SPL.backup1";
 			reg = <0x00020000 0x00020000>;
 		};
 		partition@2 {
 			label = "NAND.SPL.backup2";
 			reg = <0x00040000 0x00020000>;
 		};
 		partition@3 {
 			label = "NAND.SPL.backup3";
 			reg = <0x00060000 0x00020000>;
 		};
 		partition@4 {
 			label = "NAND.u-boot-spl-os";
 			reg = <0x00080000 0x00040000>;
 		};
 		partition@5 {
 			label = "NAND.u-boot";
 			reg = <0x000c0000 0x00100000>;
 		};
 		partition@6 {
 			label = "NAND.u-boot-env";
 			reg = <0x001c0000 0x00020000>;
 		};
 		partition@7 {
 			label = "NAND.u-boot-env.backup1";
 			reg = <0x001e0000 0x00020000>;
 		};
 		partition@8 {
 			label = "NAND.kernel";
 			reg = <0x00200000 0x00800000>;
 		};
 		partition@9 {
 			label = "NAND.file-system";
 			reg = <0x00a00000 0x0f600000>;
 		};
 	};
 };

 &usb2_phy1 {
 	phy-supply = <&ldo4_reg>;
 };

 &usb2_phy2 {
 	phy-supply = <&ldo4_reg>;
 };

 &omap_dwc3_1 {
 	extcon = <&extcon_usb1>;
 };

 &omap_dwc3_2 {
 	extcon = <&extcon_usb2>;
 };

 &usb1 {
 	dr_mode = "otg";
 };

 &usb2 {
 	dr_mode = "host";
 };

 &mmc1 {
 	status = "okay";
 	pinctrl-names = "default";
 	pinctrl-0 = <&mmc1_pins_default>;
 	vmmc_aux-supply = <&ldo1_reg>;
 	bus-width = <4>;
 	/*
 	 * SDCD signal is not being used here - using the fact that GPIO mode
 	 * is a viable alternative
 	 */
 	cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
 	max-frequency = <192000000>;
 };

 &mmc2 {
 	/* SW5-3 in ON position */
 	status = "okay";
 	pinctrl-names = "default";
 	pinctrl-0 = <&mmc2_pins_default>;

 	vmmc-supply = <&evm_3v3>;
 	bus-width = <8>;
 	ti,non-removable;
 	max-frequency = <192000000>;
 };

 &mac {
 	status = "okay";
 };

 &dcan1 {
 	status = "ok";
 };

 &qspi {
 	status = "okay";

 	spi-max-frequency = <76800000>;
 	m25p80@0 {
 		compatible = "s25fl256s1", "spi-flash";
 		spi-max-frequency = <76800000>;
 		reg = <0>;
 		spi-tx-bus-width = <1>;
 		spi-rx-bus-width = <4>;
 		#address-cells = <1>;
 		#size-cells = <1>;

 		/* MTD partition table.
 		 * The ROM checks the first four physical blocks
 		 * for a valid file to boot and the flash here is
 		 * 64KiB block size.
 		 */
 		partition@0 {
 			label = "QSPI.SPL";
 			reg = <0x00000000 0x000010000>;
 		};
 		partition@1 {
 			label = "QSPI.SPL.backup1";
 			reg = <0x00010000 0x00010000>;
 		};
 		partition@2 {
 			label = "QSPI.SPL.backup2";
 			reg = <0x00020000 0x00010000>;
 		};
 		partition@3 {
 			label = "QSPI.SPL.backup3";
 			reg = <0x00030000 0x00010000>;
 		};
 		partition@4 {
 			label = "QSPI.u-boot";
 			reg = <0x00040000 0x00100000>;
 		};
 		partition@5 {
 			label = "QSPI.u-boot-spl-os";
 			reg = <0x00140000 0x00080000>;
 		};
 		partition@6 {
 			label = "QSPI.u-boot-env";
 			reg = <0x001c0000 0x00010000>;
 		};
 		partition@7 {
 			label = "QSPI.u-boot-env.backup1";
 			reg = <0x001d0000 0x0010000>;
 		};
 		partition@8 {
 			label = "QSPI.kernel";
 			reg = <0x001e0000 0x0800000>;
 		};
 		partition@9 {
 			label = "QSPI.file-system";
 			reg = <0x009e0000 0x01620000>;
 		};
 	};
 };

 &dss {
 	status = "ok";

 	vdda_video-supply = <&ldo5_reg>;
 };

 &hdmi {
 	status = "ok";

 	port {
 		hdmi_out: endpoint {
 			remote-endpoint = <&tpd12s015_in>;
 		};
 	};
 };
	/*
	* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
	*
	* This program is free software; you can redistribute it and/or modify
	* it under the terms of the GNU General Public License version 2 as
	* published by the Free Software Foundation.
	*/
	/dts-v1/;

	#include "dra72x.dtsi"
	#include <dt-bindings/gpio/gpio.h>

	/ {
	compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";

	chosen {
	stdout-path = &uart1;
	tick-timer = &timer2;
	};

	aliases {
	display0 = &hdmi0;
	};

	evm_3v3: fixedregulator-evm_3v3 {
	compatible = "regulator-fixed";
	regulator-name = "evm_3v3";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	};

	extcon_usb1: extcon_usb1 {
	compatible = "linux,extcon-usb-gpio";
	id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
	};

	extcon_usb2: extcon_usb2 {
	compatible = "linux,extcon-usb-gpio";
	id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
	};

	hdmi0: connector {
	compatible = "hdmi-connector";
	label = "hdmi";

	type = "a";

	port {
	hdmi_connector_in: endpoint {
	remote-endpoint = <&tpd12s015_out>;
	};
	};
	};

	tpd12s015: encoder {
	compatible = "ti,tpd12s015";

	gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */
	<&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */
	<&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */

	ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;

	tpd12s015_in: endpoint {
	remote-endpoint = <&hdmi_out>;
	};
	};

	port@1 {
	reg = <1>;

	tpd12s015_out: endpoint {
	remote-endpoint = <&hdmi_connector_in>;
	};
	};
	};
	};
	};

	&dra7_pmx_core {
	mmc1_pins_default: mmc1_pins_default {
	pinctrl-single,pins = <
	0x354 (PIN_INPUT_PULLUP \| MUX_MODE0) /* mmc1_clk.clk */
	0x358 (PIN_INPUT_PULLUP \| MUX_MODE0) /* mmc1_cmd.cmd */
	0x35c (PIN_INPUT_PULLUP \| MUX_MODE0) /* mmc1_dat0.dat0 */
	0x360 (PIN_INPUT_PULLUP \| MUX_MODE0) /* mmc1_dat1.dat1 */
	0x364 (PIN_INPUT_PULLUP \| MUX_MODE0) /* mmc1_dat2.dat2 */
	0x368 (PIN_INPUT_PULLUP \| MUX_MODE0) /* mmc1_dat3.dat3 */
	>;
	};

	mmc2_pins_default: mmc2_pins_default {
	pinctrl-single,pins = <
	0x9c (PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_a23.mmc2_clk */
	0xb0 (PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
	0xa0 (PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
	0xa4 (PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
	0xa8 (PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
	0xac (PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
	0x8c (PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
	0x90 (PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
	0x94 (PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
	0x98 (PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
	>;
	};

	dcan1_pins_default: dcan1_pins_default {
	pinctrl-single,pins = <
	0x3d0 (PIN_OUTPUT_PULLUP \| MUX_MODE0) /* dcan1_tx */
	0x418 (PULL_UP \| MUX_MODE1) /* wakeup0.dcan1_rx */
	>;
	};

	dcan1_pins_sleep: dcan1_pins_sleep {
	pinctrl-single,pins = <
	0x3d0 (MUX_MODE15 \| PULL_UP) /* dcan1_tx.off */
	0x418 (MUX_MODE15 \| PULL_UP) /* wakeup0.off */
	>;
	};
	};

	&i2c1 {
	status = "okay";
	clock-frequency = <400000>;

	tps65917: tps65917@58 {
	compatible = "ti,tps65917";
	reg = <0x58>;

	interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
	interrupt-controller;
	#interrupt-cells = <2>;

	ti,system-power-controller;

	tps65917_pmic {
	compatible = "ti,tps65917-pmic";

	tps65917_regulators: regulators {
	smps1_reg: smps1 {
	/* VDD_MPU */
	regulator-name = "smps1";
	regulator-min-microvolt = <850000>;
	regulator-max-microvolt = <1250000>;
	regulator-always-on;
	regulator-boot-on;
	};

	smps2_reg: smps2 {
	/* VDD_CORE */
	regulator-name = "smps2";
	regulator-min-microvolt = <850000>;
	regulator-max-microvolt = <1060000>;
	regulator-boot-on;
	regulator-always-on;
	};

	smps3_reg: smps3 {
	/* VDD_GPU IVA DSPEVE */
	regulator-name = "smps3";
	regulator-min-microvolt = <850000>;
	regulator-max-microvolt = <1250000>;
	regulator-boot-on;
	regulator-always-on;
	};

	smps4_reg: smps4 {
	/* VDDS1V8 */
	regulator-name = "smps4";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	regulator-boot-on;
	};

	smps5_reg: smps5 {
	/* VDD_DDR */
	regulator-name = "smps5";
	regulator-min-microvolt = <1350000>;
	regulator-max-microvolt = <1350000>;
	regulator-boot-on;
	regulator-always-on;
	};

	ldo1_reg: ldo1 {
	/* LDO1_OUT --> SDIO */
	regulator-name = "ldo1";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	regulator-always-on;
	regulator-boot-on;
	regulator-allow-bypass;
	};

	ldo3_reg: ldo3 {
	/* VDDA_1V8_PHY */
	regulator-name = "ldo3";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-boot-on;
	regulator-always-on;
	};

	ldo5_reg: ldo5 {
	/* VDDA_1V8_PLL */
	regulator-name = "ldo5";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-always-on;
	regulator-boot-on;
	};

	ldo4_reg: ldo4 {
	/* VDDA_3V_USB: VDDA_USBHS33 */
	regulator-name = "ldo4";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-boot-on;
	};
	};
	};

	tps65917_power_button {
	compatible = "ti,palmas-pwrbutton";
	interrupt-parent = <&tps65917>;
	interrupts = <1 IRQ_TYPE_NONE>;
	wakeup-source;
	ti,palmas-long-press-seconds = <6>;
	};
	};

	pcf_gpio_21: gpio@21 {
	compatible = "ti,pcf8575";
	u-boot,i2c-offset-len = <0>;
	reg = <0x21>;
	lines-initial-states = <0x1408>;
	gpio-controller;
	#gpio-cells = <2>;

	interrupt-controller;
	#interrupt-cells = <2>;
	};
	};

	&i2c5 {
	status = "okay";
	clock-frequency = <400000>;

	pcf_hdmi: pcf8575@26 {
	compatible = "nxp,pcf8575";
	u-boot,i2c-offset-len = <0>;
	reg = <0x26>;
	gpio-controller;
	#gpio-cells = <2>;
	/*
	* initial state is used here to keep the mdio interface
	* selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and
	* VIN2_S0 driven high otherwise Ethernet stops working
	* VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6
	*/
	lines-initial-states = <0x0f2b>;

	p1 {
	/* vin6_sel_s0: high: VIN6, low: audio */
	gpio-hog;
	gpios = <1 GPIO_ACTIVE_HIGH>;
	output-low;
	line-name = "vin6_sel_s0";
	};
	};
	};

	&uart1 {
	status = "okay";
	interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
	<&dra7_pmx_core 0x3e0>;
	};

	&elm {
	status = "okay";
	};

	&gpmc {
	/*
	* For the existing IOdelay configuration via U-Boot we don't
	* support NAND on dra72-evm. Keep it disabled. Enabling it
	* requires a different configuration by U-Boot.
	*/
	status = "disabled";
	ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */
	nand@0,0 {
	/* To use NAND, DIP switch SW5 must be set like so:
	* SW5.1 (NAND_SELn) = ON (LOW)
	* SW5.9 (GPMC_WPN) = OFF (HIGH)
	*/
	compatible = "ti,omap2-nand";
	reg = <0 0 4>; /* device IO registers */
	interrupt-parent = <&gpmc>;
	interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
	<1 IRQ_TYPE_NONE>; /* termcount */
	rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin / / device IO registers */
	ti,nand-ecc-opt = "bch8";
	ti,elm-id = <&elm>;
	nand-bus-width = <16>;
	gpmc,device-width = <2>;
	gpmc,sync-clk-ps = <0>;
	gpmc,cs-on-ns = <0>;
	gpmc,cs-rd-off-ns = <80>;
	gpmc,cs-wr-off-ns = <80>;
	gpmc,adv-on-ns = <0>;
	gpmc,adv-rd-off-ns = <60>;
	gpmc,adv-wr-off-ns = <60>;
	gpmc,we-on-ns = <10>;
	gpmc,we-off-ns = <50>;
	gpmc,oe-on-ns = <4>;
	gpmc,oe-off-ns = <40>;
	gpmc,access-ns = <40>;
	gpmc,wr-access-ns = <80>;
	gpmc,rd-cycle-ns = <80>;
	gpmc,wr-cycle-ns = <80>;
	gpmc,bus-turnaround-ns = <0>;
	gpmc,cycle2cycle-delay-ns = <0>;
	gpmc,clk-activation-ns = <0>;
	gpmc,wait-monitoring-ns = <0>;
	gpmc,wr-data-mux-bus-ns = <0>;
	/* MTD partition table */
	/* All SPL-* partitions are sized to minimal length
	* which can be independently programmable. For
	* NAND flash this is equal to size of erase-block */
	#address-cells = <1>;
	#size-cells = <1>;
	partition@0 {
	label = "NAND.SPL";
	reg = <0x00000000 0x000020000>;
	};
	partition@1 {
	label = "NAND.SPL.backup1";
	reg = <0x00020000 0x00020000>;
	};
	partition@2 {
	label = "NAND.SPL.backup2";
	reg = <0x00040000 0x00020000>;
	};
	partition@3 {
	label = "NAND.SPL.backup3";
	reg = <0x00060000 0x00020000>;
	};
	partition@4 {
	label = "NAND.u-boot-spl-os";
	reg = <0x00080000 0x00040000>;
	};
	partition@5 {
	label = "NAND.u-boot";
	reg = <0x000c0000 0x00100000>;
	};
	partition@6 {
	label = "NAND.u-boot-env";
	reg = <0x001c0000 0x00020000>;
	};
	partition@7 {
	label = "NAND.u-boot-env.backup1";
	reg = <0x001e0000 0x00020000>;
	};
	partition@8 {
	label = "NAND.kernel";
	reg = <0x00200000 0x00800000>;
	};
	partition@9 {
	label = "NAND.file-system";
	reg = <0x00a00000 0x0f600000>;
	};
	};
	};

	&usb2_phy1 {
	phy-supply = <&ldo4_reg>;
	};

	&usb2_phy2 {
	phy-supply = <&ldo4_reg>;
	};

	&omap_dwc3_1 {
	extcon = <&extcon_usb1>;
	};

	&omap_dwc3_2 {
	extcon = <&extcon_usb2>;
	};

	&usb1 {
	dr_mode = "otg";
	};

	&usb2 {
	dr_mode = "host";
	};

	&mmc1 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mmc1_pins_default>;
	vmmc_aux-supply = <&ldo1_reg>;
	bus-width = <4>;
	/*
	* SDCD signal is not being used here - using the fact that GPIO mode
	* is a viable alternative
	*/
	cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
	max-frequency = <192000000>;
	};

	&mmc2 {
	/* SW5-3 in ON position */
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mmc2_pins_default>;

	vmmc-supply = <&evm_3v3>;
	bus-width = <8>;
	ti,non-removable;
	max-frequency = <192000000>;
	};

	&mac {
	status = "okay";
	};

	&dcan1 {
	status = "ok";
	};

	&qspi {
	status = "okay";

	spi-max-frequency = <76800000>;
	m25p80@0 {
	compatible = "s25fl256s1", "spi-flash";
	spi-max-frequency = <76800000>;
	reg = <0>;
	spi-tx-bus-width = <1>;
	spi-rx-bus-width = <4>;
	#address-cells = <1>;
	#size-cells = <1>;

	/* MTD partition table.
	* The ROM checks the first four physical blocks
	* for a valid file to boot and the flash here is
	* 64KiB block size.
	*/
	partition@0 {
	label = "QSPI.SPL";
	reg = <0x00000000 0x000010000>;
	};
	partition@1 {
	label = "QSPI.SPL.backup1";
	reg = <0x00010000 0x00010000>;
	};
	partition@2 {
	label = "QSPI.SPL.backup2";
	reg = <0x00020000 0x00010000>;
	};
	partition@3 {
	label = "QSPI.SPL.backup3";
	reg = <0x00030000 0x00010000>;
	};
	partition@4 {
	label = "QSPI.u-boot";
	reg = <0x00040000 0x00100000>;
	};
	partition@5 {
	label = "QSPI.u-boot-spl-os";
	reg = <0x00140000 0x00080000>;
	};
	partition@6 {
	label = "QSPI.u-boot-env";
	reg = <0x001c0000 0x00010000>;
	};
	partition@7 {
	label = "QSPI.u-boot-env.backup1";
	reg = <0x001d0000 0x0010000>;
	};
	partition@8 {
	label = "QSPI.kernel";
	reg = <0x001e0000 0x0800000>;
	};
	partition@9 {
	label = "QSPI.file-system";
	reg = <0x009e0000 0x01620000>;
	};
	};
	};

	&dss {
	status = "ok";

	vdda_video-supply = <&ldo5_reg>;
	};

	&hdmi {
	status = "ok";

	port {
	hdmi_out: endpoint {
	remote-endpoint = <&tpd12s015_in>;
	};
	};
	};