blob: 3bf45ef4a64f196d41f49a30ffd4b6b558ea8921 [file] [log] [blame]
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019 NXP
*/
#include "imx8mm-u-boot.dtsi"
/ {
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
u-boot,dm-spl;
};
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
};
};
&aips4 {
u-boot,dm-spl;
};
&reg_usdhc2_vmmc {
u-boot,off-on-delay-us = <20000>;
};
&pinctrl_reg_usdhc2_vmmc {
u-boot,dm-spl;
};
&pinctrl_uart2 {
u-boot,dm-spl;
};
&pinctrl_usdhc2_gpio {
u-boot,dm-spl;
};
&pinctrl_usdhc2 {
u-boot,dm-spl;
};
&pinctrl_usdhc3 {
u-boot,dm-spl;
};
&gpio1 {
u-boot,dm-spl;
};
&gpio2 {
u-boot,dm-spl;
};
&gpio3 {
u-boot,dm-spl;
};
&gpio4 {
u-boot,dm-spl;
};
&gpio5 {
u-boot,dm-spl;
};
&uart2 {
u-boot,dm-spl;
};
&usbmisc1 {
u-boot,dm-spl;
};
&usbphynop1 {
u-boot,dm-spl;
};
&usbotg1 {
u-boot,dm-spl;
};
&usdhc1 {
u-boot,dm-spl;
};
&usdhc2 {
u-boot,dm-spl;
sd-uhs-sdr104;
sd-uhs-ddr50;
assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
assigned-clock-rates = <400000000>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_400M>;
};
&usdhc3 {
u-boot,dm-spl;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
/*
* prevents voltage switch warn: driver will switch even at
* fixed voltage
*/
/delete-property/ vmmc-supply;
/delete-property/ vqmmc-supply;
assigned-clocks = <&clk IMX8MM_CLK_USDHC3>;
assigned-clock-rates = <400000000>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_400M>;
};
&i2c1 {
u-boot,dm-spl;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@25} {
u-boot,dm-spl;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
u-boot,dm-spl;
};
&pinctrl_i2c1 {
u-boot,dm-spl;
};
&pinctrl_pmic {
u-boot,dm-spl;
};
&wdog1 {
u-boot,dm-spl;
};