// SPDX-License-Identifier: GPL-2.0-or-later | |
/* | |
* T1040/T1042 Silicon/SoC Device Tree Source (pre include) | |
* | |
* Copyright 2013-2014 Freescale Semiconductor Inc. | |
*/ | |
/dts-v1/; | |
/include/ "e5500_power_isa.dtsi" | |
/ { | |
#address-cells = <2>; | |
#size-cells = <2>; | |
interrupt-parent = <&mpic>; | |
aliases { | |
ccsr = &soc; | |
dcsr = &dcsr; | |
serial0 = &serial0; | |
serial1 = &serial1; | |
serial2 = &serial2; | |
serial3 = &serial3; | |
pci0 = &pci0; | |
pci1 = &pci1; | |
pci2 = &pci2; | |
pci3 = &pci3; | |
usb0 = &usb0; | |
usb1 = &usb1; | |
sdhc = &sdhc; | |
crypto = &crypto; | |
fman0 = &fman0; | |
ethernet0 = &enet0; | |
ethernet1 = &enet1; | |
ethernet2 = &enet2; | |
ethernet3 = &enet3; | |
ethernet4 = &enet4; | |
}; | |
cpus { | |
#address-cells = <1>; | |
#size-cells = <0>; | |
cpu0: PowerPC,e5500@0 { | |
device_type = "cpu"; | |
reg = <0>; | |
clocks = <&clockgen 1 0>; | |
next-level-cache = <&L2_1>; | |
#cooling-cells = <2>; | |
L2_1: l2-cache { | |
next-level-cache = <&cpc>; | |
}; | |
}; | |
cpu1: PowerPC,e5500@1 { | |
device_type = "cpu"; | |
reg = <1>; | |
clocks = <&clockgen 1 1>; | |
next-level-cache = <&L2_2>; | |
#cooling-cells = <2>; | |
L2_2: l2-cache { | |
next-level-cache = <&cpc>; | |
}; | |
}; | |
cpu2: PowerPC,e5500@2 { | |
device_type = "cpu"; | |
reg = <2>; | |
clocks = <&clockgen 1 2>; | |
next-level-cache = <&L2_3>; | |
#cooling-cells = <2>; | |
L2_3: l2-cache { | |
next-level-cache = <&cpc>; | |
}; | |
}; | |
cpu3: PowerPC,e5500@3 { | |
device_type = "cpu"; | |
reg = <3>; | |
clocks = <&clockgen 1 3>; | |
next-level-cache = <&L2_4>; | |
#cooling-cells = <2>; | |
L2_4: l2-cache { | |
next-level-cache = <&cpc>; | |
}; | |
}; | |
}; | |
}; |