| // SPDX-License-Identifier: GPL-2.0+ |
| /* |
| * K3: ARM64 MMU setup |
| * |
| * Copyright (C) 2018-2020 Texas Instruments Incorporated - https://www.ti.com/ |
| * Lokesh Vutla <lokeshvutla@ti.com> |
| * Suman Anna <s-anna@ti.com> |
| * (This file is derived from arch/arm/mach-zynqmp/cpu.c) |
| * |
| */ |
| |
| #include <asm/system.h> |
| #include <asm/armv8/mmu.h> |
| |
| #ifdef CONFIG_SOC_K3_AM654 |
| struct mm_region am654_mem_map[] = { |
| { |
| .virt = 0x0UL, |
| .phys = 0x0UL, |
| .size = 0x80000000UL, |
| .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| PTE_BLOCK_NON_SHARE | |
| PTE_BLOCK_PXN | PTE_BLOCK_UXN |
| }, { |
| .virt = 0x80000000UL, |
| .phys = 0x80000000UL, |
| .size = 0x1e780000UL, |
| .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| PTE_BLOCK_INNER_SHARE |
| }, { |
| .virt = 0xa0000000UL, |
| .phys = 0xa0000000UL, |
| .size = 0x60000000UL, |
| .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| PTE_BLOCK_INNER_SHARE |
| }, { |
| .virt = 0x880000000UL, |
| .phys = 0x880000000UL, |
| .size = 0x80000000UL, |
| .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| PTE_BLOCK_INNER_SHARE |
| }, { |
| .virt = 0x500000000UL, |
| .phys = 0x500000000UL, |
| .size = 0x400000000UL, |
| .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| PTE_BLOCK_NON_SHARE | |
| PTE_BLOCK_PXN | PTE_BLOCK_UXN |
| }, { |
| /* List terminator */ |
| 0, |
| } |
| }; |
| |
| struct mm_region *mem_map = am654_mem_map; |
| #endif /* CONFIG_SOC_K3_AM654 */ |
| |
| #ifdef CONFIG_SOC_K3_J721E |
| |
| #ifdef CONFIG_SOC_K3_J721E_J7200 |
| struct mm_region j7200_mem_map[] = { |
| { |
| .virt = 0x0UL, |
| .phys = 0x0UL, |
| .size = 0x80000000UL, |
| .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| PTE_BLOCK_NON_SHARE | |
| PTE_BLOCK_PXN | PTE_BLOCK_UXN |
| }, { |
| .virt = 0x80000000UL, |
| .phys = 0x80000000UL, |
| .size = 0x1e780000UL, |
| .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| PTE_BLOCK_INNER_SHARE |
| }, { |
| .virt = 0xa0000000UL, |
| .phys = 0xa0000000UL, |
| .size = 0x60000000UL, |
| .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| PTE_BLOCK_INNER_SHARE |
| }, { |
| .virt = 0x880000000UL, |
| .phys = 0x880000000UL, |
| .size = 0x80000000UL, |
| .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| PTE_BLOCK_INNER_SHARE |
| }, { |
| .virt = 0x500000000UL, |
| .phys = 0x500000000UL, |
| .size = 0x400000000UL, |
| .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| PTE_BLOCK_NON_SHARE | |
| PTE_BLOCK_PXN | PTE_BLOCK_UXN |
| }, { |
| /* List terminator */ |
| 0, |
| } |
| }; |
| |
| struct mm_region *mem_map = j7200_mem_map; |
| |
| #else /* CONFIG_SOC_K3_J721E_J7200 */ |
| struct mm_region j721e_mem_map[] = { |
| { |
| .virt = 0x0UL, |
| .phys = 0x0UL, |
| .size = 0x80000000UL, |
| .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| PTE_BLOCK_NON_SHARE | |
| PTE_BLOCK_PXN | PTE_BLOCK_UXN |
| }, { |
| .virt = 0x80000000UL, |
| .phys = 0x80000000UL, |
| .size = 0x1e780000UL, |
| .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| PTE_BLOCK_INNER_SHARE |
| }, { |
| .virt = 0xa0000000UL, |
| .phys = 0xa0000000UL, |
| .size = 0x60000000UL, |
| .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| PTE_BLOCK_INNER_SHARE |
| }, { |
| .virt = 0x880000000UL, |
| .phys = 0x880000000UL, |
| .size = 0x80000000UL, |
| .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| PTE_BLOCK_INNER_SHARE |
| }, { |
| .virt = 0x500000000UL, |
| .phys = 0x500000000UL, |
| .size = 0x400000000UL, |
| .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| PTE_BLOCK_NON_SHARE | |
| PTE_BLOCK_PXN | PTE_BLOCK_UXN |
| }, { |
| /* List terminator */ |
| 0, |
| } |
| }; |
| |
| struct mm_region *mem_map = j721e_mem_map; |
| #endif /* CONFIG_SOC_K3_J721E_J7200 */ |
| |
| #endif /* CONFIG_SOC_K3_J721E */ |
| |
| #ifdef CONFIG_SOC_K3_J721S2 |
| struct mm_region j721s2_mem_map[] = { |
| { |
| .virt = 0x0UL, |
| .phys = 0x0UL, |
| .size = 0x80000000UL, |
| .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| PTE_BLOCK_NON_SHARE | |
| PTE_BLOCK_PXN | PTE_BLOCK_UXN |
| }, { |
| .virt = 0x80000000UL, |
| .phys = 0x80000000UL, |
| .size = 0x1e780000UL, |
| .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| PTE_BLOCK_INNER_SHARE |
| }, { |
| .virt = 0xa0000000UL, |
| .phys = 0xa0000000UL, |
| .size = 0x60000000UL, |
| .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| PTE_BLOCK_INNER_SHARE |
| }, { |
| .virt = 0x880000000UL, |
| .phys = 0x880000000UL, |
| .size = 0x80000000UL, |
| .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| PTE_BLOCK_INNER_SHARE |
| }, { |
| .virt = 0x500000000UL, |
| .phys = 0x500000000UL, |
| .size = 0x400000000UL, |
| .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| PTE_BLOCK_NON_SHARE | |
| PTE_BLOCK_PXN | PTE_BLOCK_UXN |
| }, { |
| /* List terminator */ |
| 0, |
| } |
| }; |
| |
| struct mm_region *mem_map = j721s2_mem_map; |
| |
| #endif /* CONFIG_SOC_K3_J721S2 */ |
| |
| #if defined(CONFIG_SOC_K3_AM625) || defined(CONFIG_SOC_K3_AM62A7) |
| |
| struct mm_region am62_mem_map[] = { |
| { |
| .virt = 0x0UL, |
| .phys = 0x0UL, |
| .size = 0x80000000UL, |
| .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| PTE_BLOCK_NON_SHARE | |
| PTE_BLOCK_PXN | PTE_BLOCK_UXN |
| }, { |
| .virt = 0x80000000UL, |
| .phys = 0x80000000UL, |
| .size = 0x1E780000UL, |
| .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| PTE_BLOCK_INNER_SHARE |
| }, { |
| .virt = 0xA0000000UL, |
| .phys = 0xA0000000UL, |
| .size = 0x60000000UL, |
| .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| PTE_BLOCK_INNER_SHARE |
| |
| }, { |
| .virt = 0x880000000UL, |
| .phys = 0x880000000UL, |
| .size = 0x80000000UL, |
| .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| PTE_BLOCK_INNER_SHARE |
| }, { |
| .virt = 0x500000000UL, |
| .phys = 0x500000000UL, |
| .size = 0x400000000UL, |
| .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| PTE_BLOCK_NON_SHARE | |
| PTE_BLOCK_PXN | PTE_BLOCK_UXN |
| }, { |
| /* List terminator */ |
| 0, |
| } |
| }; |
| |
| struct mm_region *mem_map = am62_mem_map; |
| #endif /* CONFIG_SOC_K3_AM625 || CONFIG_SOC_K3_AM62A7 */ |
| |
| #ifdef CONFIG_SOC_K3_AM642 |
| |
| struct mm_region am64_mem_map[] = { |
| { |
| .virt = 0x0UL, |
| .phys = 0x0UL, |
| .size = 0x80000000UL, |
| .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| PTE_BLOCK_NON_SHARE | |
| PTE_BLOCK_PXN | PTE_BLOCK_UXN |
| }, { |
| .virt = 0x80000000UL, |
| .phys = 0x80000000UL, |
| .size = 0x1E800000UL, |
| .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| PTE_BLOCK_INNER_SHARE |
| }, { |
| .virt = 0xA0000000UL, |
| .phys = 0xA0000000UL, |
| .size = 0x60000000UL, |
| .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| PTE_BLOCK_INNER_SHARE |
| }, { |
| .virt = 0x880000000UL, |
| .phys = 0x880000000UL, |
| .size = 0x80000000UL, |
| .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| PTE_BLOCK_INNER_SHARE |
| }, { |
| .virt = 0x500000000UL, |
| .phys = 0x500000000UL, |
| .size = 0x400000000UL, |
| .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| PTE_BLOCK_NON_SHARE | |
| PTE_BLOCK_PXN | PTE_BLOCK_UXN |
| }, { |
| /* List terminator */ |
| 0, |
| } |
| }; |
| |
| struct mm_region *mem_map = am64_mem_map; |
| #endif /* CONFIG_SOC_K3_AM642 */ |