| /* |
| * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. |
| * Copyright (C) 2016 Grinn |
| * |
| * SPDX-License-Identifier: GPL-2.0+ |
| */ |
| |
| #include <asm/arch/clock.h> |
| #include <asm/arch/iomux.h> |
| #include <asm/arch/imx-regs.h> |
| #include <asm/arch/crm_regs.h> |
| #include <asm/arch/mx6ul_pins.h> |
| #include <asm/arch/mx6-pins.h> |
| #include <asm/arch/sys_proto.h> |
| #include <asm/gpio.h> |
| #include <asm/imx-common/iomux-v3.h> |
| #include <asm/imx-common/boot_mode.h> |
| #include <asm/io.h> |
| #include <common.h> |
| #include <fsl_esdhc.h> |
| #include <linux/sizes.h> |
| #include <linux/fb.h> |
| #include <mach/litesom.h> |
| #include <miiphy.h> |
| #include <mmc.h> |
| #include <netdev.h> |
| #include <spl.h> |
| #include <usb.h> |
| #include <usb/ehci-ci.h> |
| |
| DECLARE_GLOBAL_DATA_PTR; |
| |
| #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
| PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ |
| PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
| |
| #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
| PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ |
| PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
| |
| #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ |
| PAD_CTL_SPEED_HIGH | \ |
| PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) |
| |
| #define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ |
| PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE) |
| |
| #define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) |
| |
| static iomux_v3_cfg_t const uart1_pads[] = { |
| MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), |
| MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), |
| }; |
| |
| static iomux_v3_cfg_t const sd_pads[] = { |
| MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| |
| /* CD */ |
| MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| }; |
| |
| #ifdef CONFIG_FEC_MXC |
| static iomux_v3_cfg_t const fec1_pads[] = { |
| MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL), |
| MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), |
| MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| }; |
| |
| static void setup_iomux_fec(void) |
| { |
| imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); |
| } |
| #endif |
| |
| static void setup_iomux_uart(void) |
| { |
| imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); |
| } |
| |
| #ifdef CONFIG_FSL_ESDHC |
| static struct fsl_esdhc_cfg sd_cfg = {USDHC1_BASE_ADDR, 0, 4}; |
| |
| #define SD_CD_GPIO IMX_GPIO_NR(1, 19) |
| |
| static int mmc_get_env_devno(void) |
| { |
| u32 soc_sbmr = readl(SRC_BASE_ADDR + 0x4); |
| int dev_no; |
| u32 bootsel; |
| |
| bootsel = (soc_sbmr & 0x000000FF) >> 6; |
| |
| /* If not boot from sd/mmc, use default value */ |
| if (bootsel != 1) |
| return CONFIG_SYS_MMC_ENV_DEV; |
| |
| /* BOOT_CFG2[3] and BOOT_CFG2[4] */ |
| dev_no = (soc_sbmr & 0x00001800) >> 11; |
| |
| return dev_no; |
| } |
| |
| int board_mmc_getcd(struct mmc *mmc) |
| { |
| struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; |
| int ret = 0; |
| |
| switch (cfg->esdhc_base) { |
| case USDHC1_BASE_ADDR: |
| ret = !gpio_get_value(SD_CD_GPIO); |
| break; |
| case USDHC2_BASE_ADDR: |
| ret = 1; |
| break; |
| } |
| |
| return ret; |
| } |
| |
| int board_mmc_init(bd_t *bis) |
| { |
| int ret; |
| |
| /* SD */ |
| imx_iomux_v3_setup_multiple_pads(sd_pads, ARRAY_SIZE(sd_pads)); |
| gpio_direction_input(SD_CD_GPIO); |
| sd_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); |
| |
| ret = fsl_esdhc_initialize(bis, &sd_cfg); |
| if (ret) { |
| printf("Warning: failed to initialize mmc dev 0 (SD)\n"); |
| return ret; |
| } |
| |
| return litesom_mmc_init(bis); |
| } |
| |
| static int check_mmc_autodetect(void) |
| { |
| char *autodetect_str = getenv("mmcautodetect"); |
| |
| if ((autodetect_str != NULL) && |
| (strcmp(autodetect_str, "yes") == 0)) { |
| return 1; |
| } |
| |
| return 0; |
| } |
| |
| void board_late_mmc_init(void) |
| { |
| char cmd[32]; |
| char mmcblk[32]; |
| u32 dev_no = mmc_get_env_devno(); |
| |
| if (!check_mmc_autodetect()) |
| return; |
| |
| setenv_ulong("mmcdev", dev_no); |
| |
| /* Set mmcblk env */ |
| sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", |
| dev_no); |
| setenv("mmcroot", mmcblk); |
| |
| sprintf(cmd, "mmc dev %d", dev_no); |
| run_command(cmd, 0); |
| } |
| #endif |
| |
| #ifdef CONFIG_FEC_MXC |
| int board_eth_init(bd_t *bis) |
| { |
| setup_iomux_fec(); |
| |
| return fecmxc_initialize(bis); |
| } |
| |
| static int setup_fec(void) |
| { |
| struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; |
| int ret; |
| |
| /* Use 50M anatop loopback REF_CLK1 for ENET1, clear gpr1[13], |
| set gpr1[17]*/ |
| clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, |
| IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); |
| |
| ret = enable_fec_anatop_clock(0, ENET_50MHZ); |
| if (ret) |
| return ret; |
| |
| enable_enet_clk(1); |
| |
| return 0; |
| } |
| #endif |
| |
| #ifdef CONFIG_USB_EHCI_MX6 |
| int board_usb_phy_mode(int port) |
| { |
| return USB_INIT_HOST; |
| } |
| #endif |
| |
| int board_early_init_f(void) |
| { |
| setup_iomux_uart(); |
| |
| return 0; |
| } |
| |
| int board_init(void) |
| { |
| /* Address of boot parameters */ |
| gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; |
| |
| #ifdef CONFIG_FEC_MXC |
| setup_fec(); |
| #endif |
| |
| return 0; |
| } |
| |
| #ifdef CONFIG_CMD_BMODE |
| static const struct boot_mode board_boot_modes[] = { |
| /* 4 bit bus width */ |
| {"sd", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)}, |
| {"emmc", MAKE_CFGVAL(0x60, 0x48, 0x00, 0x00)}, |
| {NULL, 0}, |
| }; |
| #endif |
| |
| int board_late_init(void) |
| { |
| #ifdef CONFIG_CMD_BMODE |
| add_board_boot_modes(board_boot_modes); |
| #endif |
| |
| #ifdef CONFIG_ENV_IS_IN_MMC |
| board_late_mmc_init(); |
| #endif |
| |
| return 0; |
| } |
| |
| int checkboard(void) |
| { |
| puts("Board: Grinn liteBoard\n"); |
| |
| return 0; |
| } |
| |
| #ifdef CONFIG_SPL_BUILD |
| void board_boot_order(u32 *spl_boot_list) |
| { |
| struct src *psrc = (struct src *)SRC_BASE_ADDR; |
| unsigned gpr10_boot = readl(&psrc->gpr10) & (1 << 28); |
| unsigned reg = gpr10_boot ? readl(&psrc->gpr9) : readl(&psrc->sbmr1); |
| unsigned port = (reg >> 11) & 0x1; |
| |
| if (port == 0) { |
| spl_boot_list[0] = BOOT_DEVICE_MMC1; |
| spl_boot_list[1] = BOOT_DEVICE_MMC2; |
| } else { |
| spl_boot_list[0] = BOOT_DEVICE_MMC2; |
| spl_boot_list[1] = BOOT_DEVICE_MMC1; |
| } |
| } |
| |
| void board_init_f(ulong dummy) |
| { |
| litesom_init_f(); |
| } |
| #endif |