commit cb0a6a1ecc8dfe4dbdad6f9376ef78879337b118
author Zhi-zhou Zhang <etou.zh@gmail.com> Tue Oct 16 15:02:08 2012 +0200
committer Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Tue Oct 16 15:02:08 2012 +0200
tree 6398daa7ee7188509950120a9377bfa91e9c478c
parent bd23b22badadcdc414a900828253961fc5ec6c39

MIPS: don't use camel-case style

Replace camel-case style with upper-case style globally.

Signed-off-by: Zhizhou Zhang <etou.zh@gmail.com>

arch/mips/cpu/xburst/cpu.c

diff --git a/arch/mips/cpu/xburst/cpu.c b/arch/mips/cpu/xburst/cpu.c
index ddcbfaa..cc190df 100644
--- a/arch/mips/cpu/xburst/cpu.c
+++ b/arch/mips/cpu/xburst/cpu.c
@@ -84,8 +84,8 @@
 	unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
 
 	for (; addr <= aend; addr += lsize) {
-		cache_op(Hit_Writeback_Inv_D, addr);
-		cache_op(Hit_Invalidate_I, addr);
+		cache_op(HIT_WRITEBACK_INV_D, addr);
+		cache_op(HIT_INVALIDATE_I, addr);
 	}
 }
 
@@ -96,7 +96,7 @@
 	unsigned long aend = (stop - 1) & ~(lsize - 1);
 
 	for (; addr <= aend; addr += lsize)
-		cache_op(Hit_Writeback_Inv_D, addr);
+		cache_op(HIT_WRITEBACK_INV_D, addr);
 }
 
 void invalidate_dcache_range(ulong start_addr, ulong stop)
@@ -106,7 +106,7 @@
 	unsigned long aend = (stop - 1) & ~(lsize - 1);
 
 	for (; addr <= aend; addr += lsize)
-		cache_op(Hit_Invalidate_D, addr);
+		cache_op(HIT_INVALIDATE_D, addr);
 }
 
 void flush_icache_all(void)
@@ -118,7 +118,7 @@
 
 	for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_ICACHE_SIZE;
 	     addr += CONFIG_SYS_CACHELINE_SIZE) {
-		cache_op(Index_Store_Tag_I, addr);
+		cache_op(INDEX_STORE_TAG_I, addr);
 	}
 
 	/* invalidate btb */
@@ -139,7 +139,7 @@
 
 	for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_DCACHE_SIZE;
 	     addr += CONFIG_SYS_CACHELINE_SIZE) {
-		cache_op(Index_Writeback_Inv_D, addr);
+		cache_op(INDEX_WRITEBACK_INV_D, addr);
 	}
 
 	__asm__ __volatile__("sync");

arch/mips/cpu/xburst/start.S

diff --git a/arch/mips/cpu/xburst/start.S b/arch/mips/cpu/xburst/start.S
index d846104..3a8280c 100644
--- a/arch/mips/cpu/xburst/start.S
+++ b/arch/mips/cpu/xburst/start.S
@@ -96,7 +96,7 @@
 	li	t0, KSEG0
 	addi	t1, t0, CONFIG_SYS_DCACHE_SIZE
 2:
-	cache	Index_Writeback_Inv_D, 0(t0)
+	cache	INDEX_WRITEBACK_INV_D, 0(t0)
 	bne	t0, t1, 2b
 	 addi	t0, CONFIG_SYS_CACHELINE_SIZE
 
@@ -106,7 +106,7 @@
 	li	t0, KSEG0
 	addi	t1, t0, CONFIG_SYS_ICACHE_SIZE
 3:
-	cache	Index_Invalidate_I, 0(t0)
+	cache	INDEX_INVALIDATE_I, 0(t0)
 	bne	t0, t1, 3b
 	 addi	t0, CONFIG_SYS_CACHELINE_SIZE