| /* |
| * Copyright 2009 Freescale Semiconductor, Inc. |
| * |
| * This file is derived from cpu/mpc85xx/cpu.c and cpu/mpc86xx/cpu.c. |
| * Basically this file contains cpu specific common code for 85xx/86xx |
| * processors. |
| * See file CREDITS for list of people who contributed to this |
| * project. |
| * |
| * This program is free software; you can redistribute it and/or |
| * modify it under the terms of the GNU General Public License as |
| * published by the Free Software Foundation; either version 2 of |
| * the License, or (at your option) any later version. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * You should have received a copy of the GNU General Public License |
| * along with this program; if not, write to the Free Software |
| * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| * MA 02111-1307 USA |
| */ |
| |
| #include <config.h> |
| #include <common.h> |
| #include <command.h> |
| #include <tsec.h> |
| #include <netdev.h> |
| #include <asm/cache.h> |
| #include <asm/io.h> |
| |
| DECLARE_GLOBAL_DATA_PTR; |
| |
| struct cpu_type cpu_type_list [] = { |
| #if defined(CONFIG_MPC85xx) |
| CPU_TYPE_ENTRY(8533, 8533, 1), |
| CPU_TYPE_ENTRY(8533, 8533_E, 1), |
| CPU_TYPE_ENTRY(8535, 8535, 1), |
| CPU_TYPE_ENTRY(8535, 8535_E, 1), |
| CPU_TYPE_ENTRY(8536, 8536, 1), |
| CPU_TYPE_ENTRY(8536, 8536_E, 1), |
| CPU_TYPE_ENTRY(8540, 8540, 1), |
| CPU_TYPE_ENTRY(8541, 8541, 1), |
| CPU_TYPE_ENTRY(8541, 8541_E, 1), |
| CPU_TYPE_ENTRY(8543, 8543, 1), |
| CPU_TYPE_ENTRY(8543, 8543_E, 1), |
| CPU_TYPE_ENTRY(8544, 8544, 1), |
| CPU_TYPE_ENTRY(8544, 8544_E, 1), |
| CPU_TYPE_ENTRY(8545, 8545, 1), |
| CPU_TYPE_ENTRY(8545, 8545_E, 1), |
| CPU_TYPE_ENTRY(8547, 8547_E, 1), |
| CPU_TYPE_ENTRY(8548, 8548, 1), |
| CPU_TYPE_ENTRY(8548, 8548_E, 1), |
| CPU_TYPE_ENTRY(8555, 8555, 1), |
| CPU_TYPE_ENTRY(8555, 8555_E, 1), |
| CPU_TYPE_ENTRY(8560, 8560, 1), |
| CPU_TYPE_ENTRY(8567, 8567, 1), |
| CPU_TYPE_ENTRY(8567, 8567_E, 1), |
| CPU_TYPE_ENTRY(8568, 8568, 1), |
| CPU_TYPE_ENTRY(8568, 8568_E, 1), |
| CPU_TYPE_ENTRY(8569, 8569, 1), |
| CPU_TYPE_ENTRY(8569, 8569_E, 1), |
| CPU_TYPE_ENTRY(8572, 8572, 2), |
| CPU_TYPE_ENTRY(8572, 8572_E, 2), |
| CPU_TYPE_ENTRY(P1011, P1011, 1), |
| CPU_TYPE_ENTRY(P1011, P1011_E, 1), |
| CPU_TYPE_ENTRY(P1020, P1020, 2), |
| CPU_TYPE_ENTRY(P1020, P1020_E, 2), |
| CPU_TYPE_ENTRY(P2010, P2010, 1), |
| CPU_TYPE_ENTRY(P2010, P2010_E, 1), |
| CPU_TYPE_ENTRY(P2020, P2020, 2), |
| CPU_TYPE_ENTRY(P2020, P2020_E, 2), |
| #elif defined(CONFIG_MPC86xx) |
| CPU_TYPE_ENTRY(8610, 8610, 1), |
| CPU_TYPE_ENTRY(8641, 8641, 2), |
| CPU_TYPE_ENTRY(8641D, 8641D, 2), |
| #endif |
| }; |
| |
| struct cpu_type *identify_cpu(u32 ver) |
| { |
| int i; |
| for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) { |
| if (cpu_type_list[i].soc_ver == ver) |
| return &cpu_type_list[i]; |
| } |
| |
| return NULL; |
| } |
| |
| int cpu_numcores() { |
| struct cpu_type *cpu; |
| cpu = gd->cpu; |
| return cpu->num_cores; |
| } |
| |
| int probecpu (void) |
| { |
| uint svr; |
| uint ver; |
| |
| svr = get_svr(); |
| ver = SVR_SOC_VER(svr); |
| |
| gd->cpu = identify_cpu(ver); |
| |
| #ifndef CONFIG_MP |
| if (cpu_numcores() > 1) { |
| puts("Unicore software on multiprocessor system!!\n" |
| "To enable mutlticore build define CONFIG_MP\n"); |
| } |
| #endif |
| return 0; |
| } |
| |
| /* |
| * Initializes on-chip ethernet controllers. |
| * to override, implement board_eth_init() |
| */ |
| int cpu_eth_init(bd_t *bis) |
| { |
| #if defined(CONFIG_ETHER_ON_FCC) |
| fec_initialize(bis); |
| #endif |
| |
| #if defined(CONFIG_UEC_ETH) |
| uec_standard_init(bis); |
| #endif |
| |
| #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_MPC85XX_FEC) |
| tsec_standard_init(bis); |
| #endif |
| |
| return 0; |
| } |