| // SPDX-License-Identifier: GPL-2.0 |
| /* |
| * Device Tree Source for AM642 SoC Family Main Domain peripherals |
| * |
| * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ |
| */ |
| |
| &cbass_main { |
| oc_sram: sram@70000000 { |
| compatible = "mmio-sram"; |
| reg = <0x00 0x70000000 0x00 0x200000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x00 0x70000000 0x200000>; |
| |
| atf-sram@0 { |
| reg = <0x0 0x1a000>; |
| }; |
| }; |
| |
| gic500: interrupt-controller@1800000 { |
| compatible = "arm,gic-v3"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| #interrupt-cells = <3>; |
| interrupt-controller; |
| reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ |
| <0x00 0x01840000 0x00 0xC0000>; /* GICR */ |
| /* |
| * vcpumntirq: |
| * virtual CPU interface maintenance interrupt |
| */ |
| interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| |
| gic_its: msi-controller@1820000 { |
| compatible = "arm,gic-v3-its"; |
| reg = <0x00 0x01820000 0x00 0x10000>; |
| socionext,synquacer-pre-its = <0x1000000 0x400000>; |
| msi-controller; |
| #msi-cells = <1>; |
| }; |
| }; |
| |
| dmss: dmss { |
| compatible = "simple-mfd"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| dma-ranges; |
| ranges; |
| |
| ti,sci-dev-id = <25>; |
| |
| secure_proxy_main: mailbox@4d000000 { |
| compatible = "ti,am654-secure-proxy"; |
| #mbox-cells = <1>; |
| reg-names = "target_data", "rt", "scfg"; |
| reg = <0x00 0x4d000000 0x00 0x80000>, |
| <0x00 0x4a600000 0x00 0x80000>, |
| <0x00 0x4a400000 0x00 0x80000>; |
| interrupt-names = "rx_012"; |
| interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| inta_main_dmss: interrupt-controller@48000000 { |
| compatible = "ti,sci-inta"; |
| reg = <0x00 0x48000000 0x00 0x100000>; |
| #interrupt-cells = <0>; |
| interrupt-controller; |
| interrupt-parent = <&gic500>; |
| msi-controller; |
| ti,sci = <&dmsc>; |
| ti,sci-dev-id = <28>; |
| ti,interrupt-ranges = <4 68 36>; |
| ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>; |
| }; |
| |
| main_bcdma: dma-controller@485c0100 { |
| compatible = "ti,am64-dmss-bcdma"; |
| reg = <0x00 0x485c0100 0x00 0x100>, |
| <0x00 0x4c000000 0x00 0x20000>, |
| <0x00 0x4a820000 0x00 0x20000>, |
| <0x00 0x4aa40000 0x00 0x20000>, |
| <0x00 0x4bc00000 0x00 0x100000>; |
| reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt"; |
| msi-parent = <&inta_main_dmss>; |
| #dma-cells = <3>; |
| |
| ti,sci = <&dmsc>; |
| ti,sci-dev-id = <26>; |
| ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */ |
| ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */ |
| ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */ |
| }; |
| |
| main_pktdma: dma-controller@485c0000 { |
| compatible = "ti,am64-dmss-pktdma"; |
| reg = <0x00 0x485c0000 0x00 0x100>, |
| <0x00 0x4a800000 0x00 0x20000>, |
| <0x00 0x4aa00000 0x00 0x40000>, |
| <0x00 0x4b800000 0x00 0x400000>; |
| reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt"; |
| msi-parent = <&inta_main_dmss>; |
| #dma-cells = <2>; |
| |
| ti,sci = <&dmsc>; |
| ti,sci-dev-id = <30>; |
| ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */ |
| <0x24>, /* CPSW_TX_CHAN */ |
| <0x25>, /* SAUL_TX_0_CHAN */ |
| <0x26>, /* SAUL_TX_1_CHAN */ |
| <0x27>, /* ICSSG_0_TX_CHAN */ |
| <0x28>; /* ICSSG_1_TX_CHAN */ |
| ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */ |
| <0x11>, /* RING_CPSW_TX_CHAN */ |
| <0x12>, /* RING_SAUL_TX_0_CHAN */ |
| <0x13>, /* RING_SAUL_TX_1_CHAN */ |
| <0x14>, /* RING_ICSSG_0_TX_CHAN */ |
| <0x15>; /* RING_ICSSG_1_TX_CHAN */ |
| ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */ |
| <0x2b>, /* CPSW_RX_CHAN */ |
| <0x2d>, /* SAUL_RX_0_CHAN */ |
| <0x2f>, /* SAUL_RX_1_CHAN */ |
| <0x31>, /* SAUL_RX_2_CHAN */ |
| <0x33>, /* SAUL_RX_3_CHAN */ |
| <0x35>, /* ICSSG_0_RX_CHAN */ |
| <0x37>; /* ICSSG_1_RX_CHAN */ |
| ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */ |
| <0x2c>, /* FLOW_CPSW_RX_CHAN */ |
| <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */ |
| <0x32>, /* FLOW_SAUL_RX_2/3_CHAN */ |
| <0x36>, /* FLOW_ICSSG_0_RX_CHAN */ |
| <0x38>; /* FLOW_ICSSG_1_RX_CHAN */ |
| }; |
| }; |
| |
| dmsc: dmsc@44043000 { |
| compatible = "ti,k2g-sci"; |
| ti,host-id = <12>; |
| mbox-names = "rx", "tx"; |
| mboxes= <&secure_proxy_main 12>, |
| <&secure_proxy_main 13>; |
| reg-names = "debug_messages"; |
| reg = <0x00 0x44043000 0x00 0xfe0>; |
| |
| k3_pds: power-controller { |
| compatible = "ti,sci-pm-domain"; |
| #power-domain-cells = <2>; |
| }; |
| |
| k3_clks: clocks { |
| compatible = "ti,k2g-sci-clk"; |
| #clock-cells = <2>; |
| }; |
| |
| k3_reset: reset-controller { |
| compatible = "ti,sci-reset"; |
| #reset-cells = <2>; |
| }; |
| }; |
| |
| main_pmx0: pinctrl@f4000 { |
| compatible = "pinctrl-single"; |
| reg = <0x00 0xf4000 0x00 0x2d0>; |
| #pinctrl-cells = <1>; |
| pinctrl-single,register-width = <32>; |
| pinctrl-single,function-mask = <0xffffffff>; |
| }; |
| |
| main_conf: syscon@43000000 { |
| compatible = "syscon", "simple-mfd"; |
| reg = <0x00 0x43000000 0x00 0x20000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x00 0x00 0x43000000 0x20000>; |
| |
| chipid@14 { |
| compatible = "ti,am654-chipid"; |
| reg = <0x00000014 0x4>; |
| }; |
| }; |
| |
| main_uart0: serial@2800000 { |
| compatible = "ti,am64-uart", "ti,am654-uart"; |
| reg = <0x00 0x02800000 0x00 0x100>; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; |
| clock-frequency = <48000000>; |
| current-speed = <115200>; |
| power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 146 0>; |
| clock-names = "fclk"; |
| }; |
| |
| main_uart1: serial@2810000 { |
| compatible = "ti,am64-uart", "ti,am654-uart"; |
| reg = <0x00 0x02810000 0x00 0x100>; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; |
| clock-frequency = <48000000>; |
| current-speed = <115200>; |
| power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 152 0>; |
| clock-names = "fclk"; |
| }; |
| |
| main_uart2: serial@2820000 { |
| compatible = "ti,am64-uart", "ti,am654-uart"; |
| reg = <0x00 0x02820000 0x00 0x100>; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; |
| clock-frequency = <48000000>; |
| current-speed = <115200>; |
| power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 153 0>; |
| clock-names = "fclk"; |
| }; |
| |
| main_uart3: serial@2830000 { |
| compatible = "ti,am64-uart", "ti,am654-uart"; |
| reg = <0x00 0x02830000 0x00 0x100>; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; |
| clock-frequency = <48000000>; |
| current-speed = <115200>; |
| power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 154 0>; |
| clock-names = "fclk"; |
| }; |
| |
| main_uart4: serial@2840000 { |
| compatible = "ti,am64-uart", "ti,am654-uart"; |
| reg = <0x00 0x02840000 0x00 0x100>; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; |
| clock-frequency = <48000000>; |
| current-speed = <115200>; |
| power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 155 0>; |
| clock-names = "fclk"; |
| }; |
| |
| main_uart5: serial@2850000 { |
| compatible = "ti,am64-uart", "ti,am654-uart"; |
| reg = <0x00 0x02850000 0x00 0x100>; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; |
| clock-frequency = <48000000>; |
| current-speed = <115200>; |
| power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 156 0>; |
| clock-names = "fclk"; |
| }; |
| |
| main_uart6: serial@2860000 { |
| compatible = "ti,am64-uart", "ti,am654-uart"; |
| reg = <0x00 0x02860000 0x00 0x100>; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; |
| clock-frequency = <48000000>; |
| current-speed = <115200>; |
| power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 158 0>; |
| clock-names = "fclk"; |
| }; |
| |
| main_i2c0: i2c@20000000 { |
| compatible = "ti,am64-i2c", "ti,omap4-i2c"; |
| reg = <0x00 0x20000000 0x00 0x100>; |
| interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 102 2>; |
| clock-names = "fck"; |
| }; |
| |
| main_i2c1: i2c@20010000 { |
| compatible = "ti,am64-i2c", "ti,omap4-i2c"; |
| reg = <0x00 0x20010000 0x00 0x100>; |
| interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 103 2>; |
| clock-names = "fck"; |
| }; |
| |
| main_i2c2: i2c@20020000 { |
| compatible = "ti,am64-i2c", "ti,omap4-i2c"; |
| reg = <0x00 0x20020000 0x00 0x100>; |
| interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 104 2>; |
| clock-names = "fck"; |
| }; |
| |
| main_i2c3: i2c@20030000 { |
| compatible = "ti,am64-i2c", "ti,omap4-i2c"; |
| reg = <0x00 0x20030000 0x00 0x100>; |
| interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 105 2>; |
| clock-names = "fck"; |
| }; |
| |
| main_spi0: spi@20100000 { |
| compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; |
| reg = <0x00 0x20100000 0x00 0x400>; |
| interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 141 0>; |
| dmas = <&main_pktdma 0xc300 0>, <&main_pktdma 0x4300 0>; |
| dma-names = "tx0", "rx0"; |
| }; |
| |
| main_spi1: spi@20110000 { |
| compatible = "ti,am654-mcspi","ti,omap4-mcspi"; |
| reg = <0x00 0x20110000 0x00 0x400>; |
| interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 142 0>; |
| }; |
| |
| main_spi2: spi@20120000 { |
| compatible = "ti,am654-mcspi","ti,omap4-mcspi"; |
| reg = <0x00 0x20120000 0x00 0x400>; |
| interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 143 0>; |
| }; |
| |
| main_spi3: spi@20130000 { |
| compatible = "ti,am654-mcspi","ti,omap4-mcspi"; |
| reg = <0x00 0x20130000 0x00 0x400>; |
| interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 144 0>; |
| }; |
| |
| main_spi4: spi@20140000 { |
| compatible = "ti,am654-mcspi","ti,omap4-mcspi"; |
| reg = <0x00 0x20140000 0x00 0x400>; |
| interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| power-domains = <&k3_pds 145 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 145 0>; |
| }; |
| |
| sdhci0: mmc@fa10000 { |
| compatible = "ti,am64-sdhci-8bit"; |
| reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>; |
| interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 57 0>, <&k3_clks 57 1>; |
| clock-names = "clk_ahb", "clk_xin"; |
| mmc-ddr-1_8v; |
| mmc-hs200-1_8v; |
| mmc-hs400-1_8v; |
| ti,trm-icp = <0x2>; |
| ti,otap-del-sel-legacy = <0x0>; |
| ti,otap-del-sel-mmc-hs = <0x0>; |
| ti,otap-del-sel-ddr52 = <0x6>; |
| ti,otap-del-sel-hs200 = <0x7>; |
| ti,otap-del-sel-hs400 = <0x4>; |
| }; |
| |
| sdhci1: mmc@fa00000 { |
| compatible = "ti,am64-sdhci-4bit"; |
| reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>; |
| interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 58 3>, <&k3_clks 58 4>; |
| clock-names = "clk_ahb", "clk_xin"; |
| ti,trm-icp = <0x2>; |
| ti,otap-del-sel-legacy = <0x0>; |
| ti,otap-del-sel-sd-hs = <0xf>; |
| ti,otap-del-sel-sdr12 = <0xf>; |
| ti,otap-del-sel-sdr25 = <0xf>; |
| ti,otap-del-sel-sdr50 = <0xc>; |
| ti,otap-del-sel-sdr104 = <0x6>; |
| ti,otap-del-sel-ddr50 = <0x9>; |
| ti,clkbuf-sel = <0x7>; |
| }; |
| |
| main_gpio0: gpio@600000 { |
| compatible = "ti,j721e-gpio", "ti,keystone-gpio"; |
| reg = <0x00 0x00600000 0x00 0x100>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupts = <77 0 IRQ_TYPE_EDGE_RISING>, |
| <77 1 IRQ_TYPE_EDGE_RISING>, |
| <77 2 IRQ_TYPE_EDGE_RISING>, |
| <77 3 IRQ_TYPE_EDGE_RISING>, |
| <77 4 IRQ_TYPE_EDGE_RISING>, |
| <77 5 IRQ_TYPE_EDGE_RISING>, |
| <77 6 IRQ_TYPE_EDGE_RISING>, |
| <77 7 IRQ_TYPE_EDGE_RISING>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| ti,ngpio = <69>; |
| ti,davinci-gpio-unbanked = <0>; |
| power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 77 0>; |
| clock-names = "gpio"; |
| }; |
| |
| main_gpio1: gpio@601000 { |
| compatible = "ti,j721e-gpio", "ti,keystone-gpio"; |
| reg = <0x00 0x00601000 0x00 0x100>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupts = <78 0 IRQ_TYPE_EDGE_RISING>, |
| <78 1 IRQ_TYPE_EDGE_RISING>, |
| <78 2 IRQ_TYPE_EDGE_RISING>, |
| <78 3 IRQ_TYPE_EDGE_RISING>, |
| <78 4 IRQ_TYPE_EDGE_RISING>, |
| <78 5 IRQ_TYPE_EDGE_RISING>, |
| <78 6 IRQ_TYPE_EDGE_RISING>, |
| <78 7 IRQ_TYPE_EDGE_RISING>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| ti,ngpio = <69>; |
| ti,davinci-gpio-unbanked = <0>; |
| power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 78 0>; |
| clock-names = "gpio"; |
| }; |
| }; |