| // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| /* |
| * sam9x60.dtsi - Device Tree Include file for SAM9X60 SoC. |
| * |
| * Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries |
| * |
| * Author: Sandeep Sheriker M <sandeepsheriker.mallikarjun@microchip.com> |
| */ |
| |
| #include "skeleton.dtsi" |
| #include <dt-bindings/dma/at91.h> |
| #include <dt-bindings/pinctrl/at91.h> |
| #include <dt-bindings/interrupt-controller/irq.h> |
| #include <dt-bindings/gpio/gpio.h> |
| #include <dt-bindings/clock/at91.h> |
| |
| /{ |
| model = "Microchip SAM9X60 SoC"; |
| compatible = "microchip,sam9x60"; |
| |
| aliases { |
| serial0 = &dbgu; |
| gpio0 = &pioA; |
| gpio1 = &pioB; |
| gpio3 = &pioD; |
| spi0 = &qspi; |
| }; |
| |
| clocks { |
| slow_xtal: slow_xtal { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <0>; |
| }; |
| |
| main_xtal: main_xtal { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <0>; |
| }; |
| }; |
| |
| ahb { |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| sdhci0: sdhci-host@80000000 { |
| compatible = "microchip,sam9x60-sdhci"; |
| reg = <0x80000000 0x300>; |
| clocks = <&sdhci0_clk>, <&sdhci0_gclk>, <&main>; |
| clock-names = "hclock", "multclk", "baseclk"; |
| bus-width = <4>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_sdhci0>; |
| }; |
| |
| apb { |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| qspi: spi@f0014000 { |
| compatible = "microchip,sam9x60-qspi"; |
| reg = <0xf0014000 0x100>, <0x70000000 0x10000000>; |
| reg-names = "qspi_base", "qspi_mmap"; |
| clocks = <&qspi_clk>, <&qspick>; |
| clock-names = "pclk", "qspick"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| flx0: flexcom@f801c600 { |
| compatible = "atmel,sama5d2-flexcom"; |
| reg = <0xf801c000 0x200>; |
| clocks = <&flx0_clk>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0xf801c000 0x800>; |
| status = "disabled"; |
| }; |
| |
| macb0: ethernet@f802c000 { |
| compatible = "cdns,sam9x60-macb", "cdns,macb"; |
| reg = <0xf802c000 0x100>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_macb0_rmii>; |
| clock-names = "hclk", "pclk"; |
| clocks = <&macb0_clk>, <&macb0_clk>; |
| status = "disabled"; |
| }; |
| |
| dbgu: serial@fffff200 { |
| compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; |
| reg = <0xfffff200 0x200>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_dbgu>; |
| clocks = <&dbgu_clk>; |
| clock-names = "usart"; |
| }; |
| |
| pinctrl { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "microchip,sam9x60-pinctrl", "simple-bus"; |
| ranges = <0xfffff400 0xfffff400 0x800>; |
| reg = <0xfffff400 0x200 /* pioA */ |
| 0xfffff600 0x200 /* pioB */ |
| 0xfffff800 0x200 /* pioC */ |
| 0xfffffa00 0x200>; /* pioD */ |
| |
| /* shared pinctrl settings */ |
| dbgu { |
| pinctrl_dbgu: dbgu-0 { |
| atmel,pins = |
| <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP |
| AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; |
| }; |
| }; |
| |
| macb0 { |
| pinctrl_macb0_rmii: macb0_rmii-0 { |
| atmel,pins = |
| <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */ |
| AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */ |
| AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A */ |
| AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */ |
| AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */ |
| AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A */ |
| AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */ |
| AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */ |
| AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */ |
| AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */ |
| }; |
| }; |
| |
| sdhci0 { |
| pinctrl_sdhci0: sdhci0 { |
| atmel,pins = |
| <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_DRIVE_STRENGTH_DEFAULT /* PA17 CK periph A with pullup */ |
| AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA16 CMD periph A with pullup */ |
| AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA15 DAT0 periph A */ |
| AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA18 DAT1 periph A with pullup */ |
| AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA19 DAT2 periph A with pullup */ |
| AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA20 DAT3 periph A with pullup */ |
| }; |
| }; |
| }; |
| |
| pioA: gpio@fffff400 { |
| compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| reg = <0xfffff400 0x200>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| clocks = <&pioA_clk>; |
| }; |
| |
| pioB: gpio@fffff600 { |
| compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| reg = <0xfffff600 0x200>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| clocks = <&pioB_clk>; |
| }; |
| |
| pioD: gpio@fffffa00 { |
| compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| reg = <0xfffffa00 0x200>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| clocks = <&pioD_clk>; |
| }; |
| |
| pmc: pmc@fffffc00 { |
| compatible = "atmel,at91sam9x5-pmc"; |
| reg = <0xfffffc00 0x200>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| main: mainck { |
| compatible = "atmel,at91sam9x5-clk-main"; |
| #clock-cells = <0>; |
| }; |
| |
| plla: pllack { |
| compatible = "microchip,sam9x60-clk-pll"; |
| #clock-cells = <0>; |
| clocks = <&main>; |
| reg = <0>; |
| atmel,clk-input-range = <8000000 24000000>; |
| #atmel,pll-clk-output-range-cells = <4>; |
| atmel,pll-clk-output-ranges = <140000000 1200000000 0 0>; |
| }; |
| |
| mck: masterck { |
| compatible = "atmel,at91sam9x5-clk-master"; |
| #clock-cells = <0>; |
| clocks = <&md_slck>, <&main>, <&plla>; |
| atmel,clk-output-range = <140000000 200000000>; |
| atmel,clk-divisors = <1 2 4 6>; |
| }; |
| |
| system: systemck { |
| compatible = "atmel,at91rm9200-clk-system"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| qspick: qspick { |
| #clock-cells = <0>; |
| reg = <19>; |
| clocks = <&mck>; |
| }; |
| }; |
| |
| periph: periphck { |
| compatible = "microchip,sam9x60-clk-peripheral"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&mck>; |
| |
| pioA_clk: pioA_clk { |
| #clock-cells = <0>; |
| reg = <2>; |
| }; |
| |
| pioB_clk: pioB_clk { |
| #clock-cells = <0>; |
| reg = <3>; |
| }; |
| |
| flx0_clk: flx0_clk { |
| #clock-cells = <0>; |
| reg = <5>; |
| }; |
| |
| pioD_clk: pioD_clk { |
| #clock-cells = <0>; |
| reg = <44>; |
| }; |
| |
| sdhci0_clk: sdhci0_clk { |
| #clock-cells = <0>; |
| reg = <12>; |
| }; |
| |
| dbgu_clk: dbgu_clk { |
| #clock-cells = <0>; |
| reg = <47>; |
| }; |
| |
| macb0_clk: macb0_clk { |
| #clock-cells = <0>; |
| reg = <24>; |
| }; |
| |
| qspi_clk: qspi_clk { |
| #clock-cells = <0>; |
| reg = <35>; |
| }; |
| }; |
| |
| generic: gck { |
| compatible = "microchip,sam9x60-clk-generated"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&md_slck>, <&td_slck>, <&main>, <&mck>, <&plla>; |
| |
| sdhci0_gclk: sdhci0_gclk { |
| #clock-cells = <0>; |
| reg = <12>; |
| }; |
| }; |
| }; |
| |
| pit: timer@fffffe40 { |
| compatible = "atmel,at91sam9260-pit"; |
| reg = <0xfffffe40 0x10>; |
| clocks = <&mck>; |
| }; |
| |
| slowckc: sckc@fffffe50 { |
| compatible = "atmel,at91sam9x5-sckc"; |
| reg = <0xfffffe50 0x4>; |
| |
| slow_osc: slow_osc { |
| compatible = "atmel,at91sam9x5-clk-slow-osc"; |
| #clock-cells = <0>; |
| clocks = <&slow_xtal>; |
| }; |
| |
| slow_rc_osc: slow_rc_osc { |
| compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; |
| #clock-cells = <0>; |
| clock-frequency = <32768>; |
| }; |
| |
| td_slck: td_slck { |
| compatible = "atmel,at91sam9x5-clk-slow"; |
| #clock-cells = <0>; |
| clocks = <&slow_rc_osc>, <&slow_osc>; |
| }; |
| |
| md_slck: md_slck { |
| compatible = "atmel,at91sam9x5-clk-slow"; |
| #clock-cells = <0>; |
| clocks = <&slow_rc_osc>; |
| }; |
| }; |
| }; |
| }; |
| |
| onewire_tm: onewire { |
| compatible = "w1-gpio"; |
| status = "disabled"; |
| }; |
| }; |