| // SPDX-License-Identifier: GPL-2.0 |
| * (C) Copyright 2019, Xilinx, Inc, |
| * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
| #include <asm/arch/sys_proto.h> |
| #include <zynqmp_firmware.h> |
| static ulong versal_align_dma_buffer(ulong *buf, u32 len) |
| if ((ulong)buf != ALIGN((ulong)buf, ARCH_DMA_MINALIGN)) { |
| new_buf = (ulong *)ALIGN((ulong)buf, ARCH_DMA_MINALIGN); |
| memcpy(new_buf, buf, len); |
| static int versal_load(xilinx_desc *desc, const void *buf, size_t bsize, |
| bin_buf = versal_align_dma_buffer((ulong *)buf, bsize); |
| debug("%s called!\n", __func__); |
| flush_dcache_range(bin_buf, bin_buf + bsize); |
| buf_lo = lower_32_bits(bin_buf); |
| buf_hi = upper_32_bits(bin_buf); |
| ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo, |
| puts("PL FPGA LOAD fail\n"); |
| struct xilinx_fpga_op versal_op = { |