| // SPDX-License-Identifier: GPL-2.0 OR MIT |
| /* |
| * Copyright (C) 2022 StarFive Technology Co., Ltd. |
| */ |
| |
| /dts-v1/; |
| #include <dt-bindings/clock/starfive,jh7110-crg.h> |
| #include <dt-bindings/reset/starfive,jh7110-crg.h> |
| |
| / { |
| compatible = "starfive,jh7110"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| S7_0: cpu@0 { |
| compatible = "sifive,s7", "riscv"; |
| reg = <0>; |
| device_type = "cpu"; |
| i-cache-block-size = <64>; |
| i-cache-sets = <64>; |
| i-cache-size = <16384>; |
| next-level-cache = <&ccache>; |
| riscv,isa = "rv64imac_zba_zbb"; |
| status = "disabled"; |
| |
| cpu0_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| U74_1: cpu@1 { |
| compatible = "sifive,u74-mc", "riscv"; |
| reg = <1>; |
| d-cache-block-size = <64>; |
| d-cache-sets = <64>; |
| d-cache-size = <32768>; |
| d-tlb-sets = <1>; |
| d-tlb-size = <40>; |
| device_type = "cpu"; |
| i-cache-block-size = <64>; |
| i-cache-sets = <64>; |
| i-cache-size = <32768>; |
| i-tlb-sets = <1>; |
| i-tlb-size = <40>; |
| mmu-type = "riscv,sv39"; |
| next-level-cache = <&ccache>; |
| riscv,isa = "rv64imafdc_zba_zbb"; |
| tlb-split; |
| |
| cpu1_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| U74_2: cpu@2 { |
| compatible = "sifive,u74-mc", "riscv"; |
| reg = <2>; |
| d-cache-block-size = <64>; |
| d-cache-sets = <64>; |
| d-cache-size = <32768>; |
| d-tlb-sets = <1>; |
| d-tlb-size = <40>; |
| device_type = "cpu"; |
| i-cache-block-size = <64>; |
| i-cache-sets = <64>; |
| i-cache-size = <32768>; |
| i-tlb-sets = <1>; |
| i-tlb-size = <40>; |
| mmu-type = "riscv,sv39"; |
| next-level-cache = <&ccache>; |
| riscv,isa = "rv64imafdc_zba_zbb"; |
| tlb-split; |
| |
| cpu2_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| U74_3: cpu@3 { |
| compatible = "sifive,u74-mc", "riscv"; |
| reg = <3>; |
| d-cache-block-size = <64>; |
| d-cache-sets = <64>; |
| d-cache-size = <32768>; |
| d-tlb-sets = <1>; |
| d-tlb-size = <40>; |
| device_type = "cpu"; |
| i-cache-block-size = <64>; |
| i-cache-sets = <64>; |
| i-cache-size = <32768>; |
| i-tlb-sets = <1>; |
| i-tlb-size = <40>; |
| mmu-type = "riscv,sv39"; |
| next-level-cache = <&ccache>; |
| riscv,isa = "rv64imafdc_zba_zbb"; |
| tlb-split; |
| |
| cpu3_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| U74_4: cpu@4 { |
| compatible = "sifive,u74-mc", "riscv"; |
| reg = <4>; |
| d-cache-block-size = <64>; |
| d-cache-sets = <64>; |
| d-cache-size = <32768>; |
| d-tlb-sets = <1>; |
| d-tlb-size = <40>; |
| device_type = "cpu"; |
| i-cache-block-size = <64>; |
| i-cache-sets = <64>; |
| i-cache-size = <32768>; |
| i-tlb-sets = <1>; |
| i-tlb-size = <40>; |
| mmu-type = "riscv,sv39"; |
| next-level-cache = <&ccache>; |
| riscv,isa = "rv64imafdc_zba_zbb"; |
| tlb-split; |
| |
| cpu4_intc: interrupt-controller { |
| compatible = "riscv,cpu-intc"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| cpu-map { |
| cluster0 { |
| core0 { |
| cpu = <&S7_0>; |
| }; |
| |
| core1 { |
| cpu = <&U74_1>; |
| }; |
| |
| core2 { |
| cpu = <&U74_2>; |
| }; |
| |
| core3 { |
| cpu = <&U74_3>; |
| }; |
| |
| core4 { |
| cpu = <&U74_4>; |
| }; |
| }; |
| }; |
| }; |
| |
| timer { |
| compatible = "riscv,timer"; |
| interrupts-extended = <&cpu0_intc 5>, |
| <&cpu1_intc 5>, |
| <&cpu2_intc 5>, |
| <&cpu3_intc 5>, |
| <&cpu4_intc 5>; |
| }; |
| |
| osc: oscillator { |
| compatible = "fixed-clock"; |
| clock-output-names = "osc"; |
| #clock-cells = <0>; |
| }; |
| |
| rtc_osc: rtc-oscillator { |
| compatible = "fixed-clock"; |
| clock-output-names = "rtc_osc"; |
| #clock-cells = <0>; |
| }; |
| |
| gmac0_rmii_refin: gmac0-rmii-refin-clock { |
| compatible = "fixed-clock"; |
| clock-output-names = "gmac0_rmii_refin"; |
| #clock-cells = <0>; |
| }; |
| |
| gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock { |
| compatible = "fixed-clock"; |
| clock-output-names = "gmac0_rgmii_rxin"; |
| #clock-cells = <0>; |
| }; |
| |
| gmac1_rmii_refin: gmac1-rmii-refin-clock { |
| compatible = "fixed-clock"; |
| clock-output-names = "gmac1_rmii_refin"; |
| #clock-cells = <0>; |
| }; |
| |
| gmac1_rgmii_rxin: gmac1-rgmii-rxin-clock { |
| compatible = "fixed-clock"; |
| clock-output-names = "gmac1_rgmii_rxin"; |
| #clock-cells = <0>; |
| }; |
| |
| i2stx_bclk_ext: i2stx-bclk-ext-clock { |
| compatible = "fixed-clock"; |
| clock-output-names = "i2stx_bclk_ext"; |
| #clock-cells = <0>; |
| }; |
| |
| i2stx_lrck_ext: i2stx-lrck-ext-clock { |
| compatible = "fixed-clock"; |
| clock-output-names = "i2stx_lrck_ext"; |
| #clock-cells = <0>; |
| }; |
| |
| i2srx_bclk_ext: i2srx-bclk-ext-clock { |
| compatible = "fixed-clock"; |
| clock-output-names = "i2srx_bclk_ext"; |
| #clock-cells = <0>; |
| }; |
| |
| i2srx_lrck_ext: i2srx-lrck-ext-clock { |
| compatible = "fixed-clock"; |
| clock-output-names = "i2srx_lrck_ext"; |
| #clock-cells = <0>; |
| }; |
| |
| tdm_ext: tdm-ext-clock { |
| compatible = "fixed-clock"; |
| clock-output-names = "tdm_ext"; |
| #clock-cells = <0>; |
| }; |
| |
| mclk_ext: mclk-ext-clock { |
| compatible = "fixed-clock"; |
| clock-output-names = "mclk_ext"; |
| #clock-cells = <0>; |
| }; |
| |
| stmmac_axi_setup: stmmac-axi-config { |
| snps,lpi_en; |
| snps,wr_osr_lmt = <4>; |
| snps,rd_osr_lmt = <4>; |
| snps,blen = <256 128 64 32 0 0 0>; |
| }; |
| |
| soc { |
| compatible = "simple-bus"; |
| interrupt-parent = <&plic>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| clint: timer@2000000 { |
| compatible = "starfive,jh7110-clint", "sifive,clint0"; |
| reg = <0x0 0x2000000 0x0 0x10000>; |
| interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, |
| <&cpu1_intc 3>, <&cpu1_intc 7>, |
| <&cpu2_intc 3>, <&cpu2_intc 7>, |
| <&cpu3_intc 3>, <&cpu3_intc 7>, |
| <&cpu4_intc 3>, <&cpu4_intc 7>; |
| }; |
| |
| plic: interrupt-controller@c000000 { |
| compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0"; |
| reg = <0x0 0xc000000 0x0 0x4000000>; |
| interrupts-extended = <&cpu0_intc 11>, |
| <&cpu1_intc 11>, <&cpu1_intc 9>, |
| <&cpu2_intc 11>, <&cpu2_intc 9>, |
| <&cpu3_intc 11>, <&cpu3_intc 9>, |
| <&cpu4_intc 11>, <&cpu4_intc 9>; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| #address-cells = <0>; |
| riscv,ndev = <136>; |
| }; |
| |
| ccache: cache-controller@2010000 { |
| compatible = "starfive,jh7110-ccache", "sifive,ccache0", "cache"; |
| reg = <0x0 0x2010000 0x0 0x4000>; |
| interrupts = <1>, <3>, <4>, <2>; |
| cache-block-size = <64>; |
| cache-level = <2>; |
| cache-sets = <2048>; |
| cache-size = <2097152>; |
| cache-unified; |
| }; |
| |
| uart0: serial@10000000 { |
| compatible = "snps,dw-apb-uart"; |
| reg = <0x0 0x10000000 0x0 0x10000>; |
| clocks = <&syscrg JH7110_SYSCLK_UART0_CORE>, |
| <&syscrg JH7110_SYSCLK_UART0_APB>; |
| clock-names = "baudclk", "apb_pclk"; |
| resets = <&syscrg JH7110_SYSRST_UART0_APB>, |
| <&syscrg JH7110_SYSRST_UART0_CORE>; |
| interrupts = <32>; |
| reg-io-width = <4>; |
| reg-shift = <2>; |
| status = "disabled"; |
| }; |
| |
| uart1: serial@10010000 { |
| compatible = "snps,dw-apb-uart"; |
| reg = <0x0 0x10010000 0x0 0x10000>; |
| clocks = <&syscrg JH7110_SYSCLK_UART1_CORE>, |
| <&syscrg JH7110_SYSCLK_UART1_APB>; |
| clock-names = "baudclk", "apb_pclk"; |
| resets = <&syscrg JH7110_SYSRST_UART1_APB>, |
| <&syscrg JH7110_SYSRST_UART1_CORE>; |
| interrupts = <33>; |
| reg-io-width = <4>; |
| reg-shift = <2>; |
| status = "disabled"; |
| }; |
| |
| uart2: serial@10020000 { |
| compatible = "snps,dw-apb-uart"; |
| reg = <0x0 0x10020000 0x0 0x10000>; |
| clocks = <&syscrg JH7110_SYSCLK_UART2_CORE>, |
| <&syscrg JH7110_SYSCLK_UART2_APB>; |
| clock-names = "baudclk", "apb_pclk"; |
| resets = <&syscrg JH7110_SYSRST_UART2_APB>, |
| <&syscrg JH7110_SYSRST_UART2_CORE>; |
| interrupts = <34>; |
| reg-io-width = <4>; |
| reg-shift = <2>; |
| status = "disabled"; |
| }; |
| |
| i2c0: i2c@10030000 { |
| compatible = "snps,designware-i2c"; |
| reg = <0x0 0x10030000 0x0 0x10000>; |
| clocks = <&syscrg JH7110_SYSCLK_I2C0_APB>; |
| clock-names = "ref"; |
| resets = <&syscrg JH7110_SYSRST_I2C0_APB>; |
| interrupts = <35>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@10040000 { |
| compatible = "snps,designware-i2c"; |
| reg = <0x0 0x10040000 0x0 0x10000>; |
| clocks = <&syscrg JH7110_SYSCLK_I2C1_APB>; |
| clock-names = "ref"; |
| resets = <&syscrg JH7110_SYSRST_I2C1_APB>; |
| interrupts = <36>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c2: i2c@10050000 { |
| compatible = "snps,designware-i2c"; |
| reg = <0x0 0x10050000 0x0 0x10000>; |
| clocks = <&syscrg JH7110_SYSCLK_I2C2_APB>; |
| clock-names = "ref"; |
| resets = <&syscrg JH7110_SYSRST_I2C2_APB>; |
| interrupts = <37>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| stgcrg: clock-controller@10230000 { |
| compatible = "starfive,jh7110-stgcrg"; |
| reg = <0x0 0x10230000 0x0 0x10000>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| stg_syscon: stg_syscon@10240000 { |
| compatible = "starfive,jh7110-stg-syscon","syscon"; |
| reg = <0x0 0x10240000 0x0 0x1000>; |
| }; |
| |
| uart3: serial@12000000 { |
| compatible = "snps,dw-apb-uart"; |
| reg = <0x0 0x12000000 0x0 0x10000>; |
| clocks = <&syscrg JH7110_SYSCLK_UART3_CORE>, |
| <&syscrg JH7110_SYSCLK_UART3_APB>; |
| clock-names = "baudclk", "apb_pclk"; |
| resets = <&syscrg JH7110_SYSRST_UART3_APB>, |
| <&syscrg JH7110_SYSRST_UART3_CORE>; |
| interrupts = <45>; |
| reg-io-width = <4>; |
| reg-shift = <2>; |
| status = "disabled"; |
| }; |
| |
| uart4: serial@12010000 { |
| compatible = "snps,dw-apb-uart"; |
| reg = <0x0 0x12010000 0x0 0x10000>; |
| clocks = <&syscrg JH7110_SYSCLK_UART4_CORE>, |
| <&syscrg JH7110_SYSCLK_UART4_APB>; |
| clock-names = "baudclk", "apb_pclk"; |
| resets = <&syscrg JH7110_SYSRST_UART4_APB>, |
| <&syscrg JH7110_SYSRST_UART4_CORE>; |
| interrupts = <46>; |
| reg-io-width = <4>; |
| reg-shift = <2>; |
| status = "disabled"; |
| }; |
| |
| uart5: serial@12020000 { |
| compatible = "snps,dw-apb-uart"; |
| reg = <0x0 0x12020000 0x0 0x10000>; |
| clocks = <&syscrg JH7110_SYSCLK_UART5_CORE>, |
| <&syscrg JH7110_SYSCLK_UART5_APB>; |
| clock-names = "baudclk", "apb_pclk"; |
| resets = <&syscrg JH7110_SYSRST_UART5_APB>, |
| <&syscrg JH7110_SYSRST_UART5_CORE>; |
| interrupts = <47>; |
| reg-io-width = <4>; |
| reg-shift = <2>; |
| status = "disabled"; |
| }; |
| |
| i2c3: i2c@12030000 { |
| compatible = "snps,designware-i2c"; |
| reg = <0x0 0x12030000 0x0 0x10000>; |
| clocks = <&syscrg JH7110_SYSCLK_I2C3_APB>; |
| clock-names = "ref"; |
| resets = <&syscrg JH7110_SYSRST_I2C3_APB>; |
| interrupts = <48>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c4: i2c@12040000 { |
| compatible = "snps,designware-i2c"; |
| reg = <0x0 0x12040000 0x0 0x10000>; |
| clocks = <&syscrg JH7110_SYSCLK_I2C4_APB>; |
| clock-names = "ref"; |
| resets = <&syscrg JH7110_SYSRST_I2C4_APB>; |
| interrupts = <49>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c5: i2c@12050000 { |
| compatible = "snps,designware-i2c"; |
| reg = <0x0 0x12050000 0x0 0x10000>; |
| clocks = <&syscrg JH7110_SYSCLK_I2C5_APB>; |
| clock-names = "ref"; |
| resets = <&syscrg JH7110_SYSRST_I2C5_APB>; |
| interrupts = <50>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c6: i2c@12060000 { |
| compatible = "snps,designware-i2c"; |
| reg = <0x0 0x12060000 0x0 0x10000>; |
| clocks = <&syscrg JH7110_SYSCLK_I2C6_APB>; |
| clock-names = "ref"; |
| resets = <&syscrg JH7110_SYSRST_I2C6_APB>; |
| interrupts = <51>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| qspi: spi@13010000 { |
| compatible = "cdns,qspi-nor"; |
| reg = <0x0 0x13010000 0x0 0x10000 |
| 0x0 0x21000000 0x0 0x400000>; |
| clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>; |
| clock-names = "clk_ref"; |
| resets = <&syscrg JH7110_SYSRST_QSPI_APB>, |
| <&syscrg JH7110_SYSRST_QSPI_AHB>, |
| <&syscrg JH7110_SYSRST_QSPI_REF>; |
| reset-names = "rst_apb", "rst_ahb", "rst_ref"; |
| cdns,fifo-depth = <256>; |
| cdns,fifo-width = <4>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| |
| syscrg: clock-controller@13020000 { |
| compatible = "starfive,jh7110-syscrg"; |
| reg = <0x0 0x13020000 0x0 0x10000>; |
| clocks = <&osc>, <&gmac1_rmii_refin>, |
| <&gmac1_rgmii_rxin>, |
| <&i2stx_bclk_ext>, <&i2stx_lrck_ext>, |
| <&i2srx_bclk_ext>, <&i2srx_lrck_ext>, |
| <&tdm_ext>, <&mclk_ext>, |
| <&pllclk JH7110_SYSCLK_PLL0_OUT>, |
| <&pllclk JH7110_SYSCLK_PLL1_OUT>, |
| <&pllclk JH7110_SYSCLK_PLL2_OUT>; |
| clock-names = "osc", "gmac1_rmii_refin", |
| "gmac1_rgmii_rxin", |
| "i2stx_bclk_ext", "i2stx_lrck_ext", |
| "i2srx_bclk_ext", "i2srx_lrck_ext", |
| "tdm_ext", "mclk_ext", |
| "pll0_out", "pll1_out", "pll2_out"; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| sys_syscon: sys_syscon@13030000 { |
| compatible = "starfive,jh7110-sys-syscon","syscon", "simple-mfd"; |
| reg = <0x0 0x13030000 0x0 0x1000>; |
| |
| pllclk: clock-controller { |
| compatible = "starfive,jh7110-pll"; |
| clocks = <&osc>; |
| #clock-cells = <1>; |
| }; |
| }; |
| |
| sysgpio: pinctrl@13040000 { |
| compatible = "starfive,jh7110-sys-pinctrl"; |
| reg = <0x0 0x13040000 0x0 0x10000>; |
| clocks = <&syscrg JH7110_SYSCLK_IOMUX_APB>; |
| resets = <&syscrg JH7110_SYSRST_IOMUX_APB>; |
| interrupts = <86>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| }; |
| |
| mmc0: mmc@16010000 { |
| compatible = "starfive,jh7110-mmc"; |
| reg = <0x0 0x16010000 0x0 0x10000>; |
| clocks = <&syscrg JH7110_SYSCLK_SDIO0_AHB>, |
| <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>; |
| clock-names = "biu", "ciu"; |
| resets = <&syscrg JH7110_SYSRST_SDIO0_AHB>; |
| reset-names = "reset"; |
| interrupts = <74>; |
| fifo-depth = <32>; |
| fifo-watermark-aligned; |
| data-addr = <0>; |
| starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>; |
| status = "disabled"; |
| }; |
| |
| mmc1: mmc@16020000 { |
| compatible = "starfive,jh7110-mmc"; |
| reg = <0x0 0x16020000 0x0 0x10000>; |
| clocks = <&syscrg JH7110_SYSCLK_SDIO1_AHB>, |
| <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>; |
| clock-names = "biu", "ciu"; |
| resets = <&syscrg JH7110_SYSRST_SDIO1_AHB>; |
| reset-names = "reset"; |
| interrupts = <75>; |
| fifo-depth = <32>; |
| fifo-watermark-aligned; |
| data-addr = <0>; |
| starfive,sysreg = <&sys_syscon 0x9c 0x1 0x3e>; |
| status = "disabled"; |
| }; |
| |
| gmac0: ethernet@16030000 { |
| compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20"; |
| reg = <0x0 0x16030000 0x0 0x10000>; |
| clocks = <&aoncrg JH7110_AONCLK_GMAC0_AXI>, |
| <&aoncrg JH7110_AONCLK_GMAC0_AHB>, |
| <&syscrg JH7110_SYSCLK_GMAC0_PTP>, |
| <&aoncrg JH7110_AONCLK_GMAC0_TX_INV>, |
| <&syscrg JH7110_SYSCLK_GMAC0_GTXC>; |
| clock-names = "stmmaceth", "pclk", "ptp_ref", |
| "tx", "gtx"; |
| resets = <&aoncrg JH7110_AONRST_GMAC0_AXI>, |
| <&aoncrg JH7110_AONRST_GMAC0_AHB>; |
| reset-names = "stmmaceth", "ahb"; |
| interrupts = <7>, <6>, <5>; |
| interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; |
| snps,multicast-filter-bins = <64>; |
| snps,perfect-filter-entries = <8>; |
| rx-fifo-depth = <2048>; |
| tx-fifo-depth = <2048>; |
| snps,fixed-burst; |
| snps,no-pbl-x8; |
| snps,force_thresh_dma_mode; |
| snps,axi-config = <&stmmac_axi_setup>; |
| snps,tso; |
| snps,en-tx-lpi-clockgating; |
| snps,txpbl = <16>; |
| snps,rxpbl = <16>; |
| starfive,syscon = <&aon_syscon 0xc 0x12>; |
| status = "disabled"; |
| }; |
| |
| gmac1: ethernet@16040000 { |
| compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20"; |
| reg = <0x0 0x16040000 0x0 0x10000>; |
| clocks = <&syscrg JH7110_SYSCLK_GMAC1_AXI>, |
| <&syscrg JH7110_SYSCLK_GMAC1_AHB>, |
| <&syscrg JH7110_SYSCLK_GMAC1_PTP>, |
| <&syscrg JH7110_SYSCLK_GMAC1_TX_INV>, |
| <&syscrg JH7110_SYSCLK_GMAC1_GTXC>; |
| clock-names = "stmmaceth", "pclk", "ptp_ref", |
| "tx", "gtx"; |
| resets = <&syscrg JH7110_SYSRST_GMAC1_AXI>, |
| <&syscrg JH7110_SYSRST_GMAC1_AHB>; |
| reset-names = "stmmaceth", "ahb"; |
| interrupts = <78>, <77>, <76>; |
| interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; |
| snps,multicast-filter-bins = <64>; |
| snps,perfect-filter-entries = <8>; |
| rx-fifo-depth = <2048>; |
| tx-fifo-depth = <2048>; |
| snps,fixed-burst; |
| snps,no-pbl-x8; |
| snps,force_thresh_dma_mode; |
| snps,axi-config = <&stmmac_axi_setup>; |
| snps,tso; |
| snps,en-tx-lpi-clockgating; |
| snps,txpbl = <16>; |
| snps,rxpbl = <16>; |
| starfive,syscon = <&sys_syscon 0x90 0x2>; |
| status = "disabled"; |
| }; |
| |
| aoncrg: clock-controller@17000000 { |
| compatible = "starfive,jh7110-aoncrg"; |
| reg = <0x0 0x17000000 0x0 0x10000>; |
| clocks = <&osc>, <&rtc_osc>, |
| <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>, |
| <&syscrg JH7110_SYSCLK_STG_AXIAHB>, |
| <&syscrg JH7110_SYSCLK_APB_BUS>, |
| <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>; |
| clock-names = "osc", "rtc_osc", "gmac0_rmii_refin", |
| "gmac0_rgmii_rxin", "stg_axiahb", |
| "apb_bus", "gmac0_gtxclk"; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| aon_syscon: aon_syscon@17010000 { |
| compatible = "starfive,jh7110-aon-syscon","syscon"; |
| reg = <0x0 0x17010000 0x0 0x1000>; |
| }; |
| |
| aongpio: pinctrl@17020000 { |
| compatible = "starfive,jh7110-aon-pinctrl"; |
| reg = <0x0 0x17020000 0x0 0x10000>; |
| resets = <&aoncrg JH7110_AONRST_IOMUX>; |
| interrupts = <85>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| }; |
| |
| pcie0: pcie@2b000000 { |
| compatible = "starfive,jh7110-pcie"; |
| reg = <0x0 0x2b000000 0x0 0x1000000 |
| 0x9 0x40000000 0x0 0x10000000>; |
| reg-names = "reg", "config"; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| #interrupt-cells = <1>; |
| ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>, |
| <0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>; |
| interrupts = <56>; |
| interrupt-parent = <&plic>; |
| interrupt-map-mask = <0x0 0x0 0x0 0x7>; |
| interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>, |
| <0x0 0x0 0x0 0x2 &plic 0x2>, |
| <0x0 0x0 0x0 0x3 &plic 0x3>, |
| <0x0 0x0 0x0 0x4 &plic 0x4>; |
| msi-parent = <&plic>; |
| device_type = "pci"; |
| starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130 0x1b8>; |
| bus-range = <0x0 0xff>; |
| clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>, |
| <&stgcrg JH7110_STGCLK_PCIE0_TL>, |
| <&stgcrg JH7110_STGCLK_PCIE0_AXI>, |
| <&stgcrg JH7110_STGCLK_PCIE0_APB>; |
| clock-names = "noc", "tl", "axi", "apb"; |
| resets = <&stgcrg JH7110_STGRST_PCIE0_MST0>, |
| <&stgcrg JH7110_STGRST_PCIE0_SLV0>, |
| <&stgcrg JH7110_STGRST_PCIE0_SLV>, |
| <&stgcrg JH7110_STGRST_PCIE0_BRG>, |
| <&stgcrg JH7110_STGRST_PCIE0_CORE>, |
| <&stgcrg JH7110_STGRST_PCIE0_APB>; |
| reset-names = "mst0", "slv0", "slv", "brg", |
| "core", "apb"; |
| status = "disabled"; |
| }; |
| |
| pcie1: pcie@2c000000 { |
| compatible = "starfive,jh7110-pcie"; |
| reg = <0x0 0x2c000000 0x0 0x1000000 |
| 0x9 0xc0000000 0x0 0x10000000>; |
| reg-names = "reg", "config"; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| #interrupt-cells = <1>; |
| ranges = <0x82000000 0x0 0x38000000 0x0 0x38000000 0x0 0x08000000>, |
| <0xc3000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>; |
| interrupts = <57>; |
| interrupt-parent = <&plic>; |
| interrupt-map-mask = <0x0 0x0 0x0 0x7>; |
| interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>, |
| <0x0 0x0 0x0 0x2 &plic 0x2>, |
| <0x0 0x0 0x0 0x3 &plic 0x3>, |
| <0x0 0x0 0x0 0x4 &plic 0x4>; |
| msi-parent = <&plic>; |
| device_type = "pci"; |
| starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0 0x368>; |
| bus-range = <0x0 0xff>; |
| clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>, |
| <&stgcrg JH7110_STGCLK_PCIE1_TL>, |
| <&stgcrg JH7110_STGCLK_PCIE1_AXI>, |
| <&stgcrg JH7110_STGCLK_PCIE1_APB>; |
| clock-names = "noc", "tl", "axi", "apb"; |
| resets = <&stgcrg JH7110_STGRST_PCIE1_MST0>, |
| <&stgcrg JH7110_STGRST_PCIE1_SLV0>, |
| <&stgcrg JH7110_STGRST_PCIE1_SLV>, |
| <&stgcrg JH7110_STGRST_PCIE1_BRG>, |
| <&stgcrg JH7110_STGRST_PCIE1_CORE>, |
| <&stgcrg JH7110_STGRST_PCIE1_APB>; |
| reset-names = "mst0", "slv0", "slv", "brg", |
| "core", "apb"; |
| status = "disabled"; |
| }; |
| }; |
| }; |