| // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| /* |
| * Device Tree file for NXP LS1028A RDB Board. |
| * |
| * Copyright 2018-2021 NXP |
| * |
| * Harninder Rai <harninder.rai@nxp.com> |
| * |
| */ |
| |
| /dts-v1/; |
| #include "fsl-ls1028a.dtsi" |
| |
| / { |
| model = "LS1028A RDB Board"; |
| compatible = "fsl,ls1028a-rdb", "fsl,ls1028a"; |
| |
| aliases { |
| crypto = &crypto; |
| serial0 = &duart0; |
| serial1 = &duart1; |
| mmc0 = &esdhc; |
| mmc1 = &esdhc1; |
| rtc1 = &ftm_alarm0; |
| spi0 = &fspi; |
| ethernet0 = &enetc_port0; |
| ethernet1 = &enetc_port2; |
| ethernet2 = &mscc_felix_port0; |
| ethernet3 = &mscc_felix_port1; |
| ethernet4 = &mscc_felix_port2; |
| ethernet5 = &mscc_felix_port3; |
| }; |
| |
| chosen { |
| stdout-path = "serial0:115200n8"; |
| }; |
| |
| memory@80000000 { |
| device_type = "memory"; |
| reg = <0x0 0x80000000 0x1 0x0000000>; |
| }; |
| |
| sys_mclk: clock-mclk { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <25000000>; |
| }; |
| |
| reg_1p8v: regulator-1p8v { |
| compatible = "regulator-fixed"; |
| regulator-name = "1P8V"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <1800000>; |
| regulator-always-on; |
| }; |
| |
| sb_3v3: regulator-sb3v3 { |
| compatible = "regulator-fixed"; |
| regulator-name = "3v3_vbus"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| sound { |
| compatible = "simple-audio-card"; |
| simple-audio-card,format = "i2s"; |
| simple-audio-card,widgets = |
| "Microphone", "Microphone Jack", |
| "Headphone", "Headphone Jack", |
| "Speaker", "Speaker Ext", |
| "Line", "Line In Jack"; |
| simple-audio-card,routing = |
| "MIC_IN", "Microphone Jack", |
| "Microphone Jack", "Mic Bias", |
| "LINE_IN", "Line In Jack", |
| "Headphone Jack", "HP_OUT", |
| "Speaker Ext", "LINE_OUT"; |
| |
| simple-audio-card,cpu { |
| sound-dai = <&sai4>; |
| frame-master; |
| bitclock-master; |
| }; |
| |
| simple-audio-card,codec { |
| sound-dai = <&sgtl5000>; |
| frame-master; |
| bitclock-master; |
| system-clock-frequency = <25000000>; |
| }; |
| }; |
| }; |
| |
| &can0 { |
| status = "okay"; |
| |
| can-transceiver { |
| max-bitrate = <5000000>; |
| }; |
| }; |
| |
| &can1 { |
| status = "okay"; |
| |
| can-transceiver { |
| max-bitrate = <5000000>; |
| }; |
| }; |
| |
| &duart0 { |
| status = "okay"; |
| }; |
| |
| &duart1 { |
| status = "okay"; |
| }; |
| |
| &enetc_mdio_pf3 { |
| sgmii_phy0: ethernet-phy@2 { |
| reg = <0x2>; |
| }; |
| |
| /* VSC8514 QSGMII quad PHY */ |
| qsgmii_phy0: ethernet-phy@10 { |
| reg = <0x10>; |
| }; |
| |
| qsgmii_phy1: ethernet-phy@11 { |
| reg = <0x11>; |
| }; |
| |
| qsgmii_phy2: ethernet-phy@12 { |
| reg = <0x12>; |
| }; |
| |
| qsgmii_phy3: ethernet-phy@13 { |
| reg = <0x13>; |
| }; |
| }; |
| |
| &enetc_port0 { |
| phy-handle = <&sgmii_phy0>; |
| phy-mode = "sgmii"; |
| managed = "in-band-status"; |
| status = "okay"; |
| }; |
| |
| &enetc_port2 { |
| status = "okay"; |
| }; |
| |
| &esdhc { |
| sd-uhs-sdr104; |
| sd-uhs-sdr50; |
| sd-uhs-sdr25; |
| sd-uhs-sdr12; |
| status = "okay"; |
| }; |
| |
| &esdhc1 { |
| mmc-hs200-1_8v; |
| mmc-hs400-1_8v; |
| bus-width = <8>; |
| status = "okay"; |
| }; |
| |
| &fspi { |
| status = "okay"; |
| |
| mt35xu02g0: flash@0 { |
| compatible = "jedec,spi-nor"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| spi-max-frequency = <50000000>; |
| /* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */ |
| spi-rx-bus-width = <8>; /* 8 SPI Rx lines */ |
| spi-tx-bus-width = <1>; /* 1 SPI Tx line */ |
| reg = <0>; |
| }; |
| }; |
| |
| &i2c0 { |
| status = "okay"; |
| |
| i2c-mux@77 { |
| compatible = "nxp,pca9847"; |
| reg = <0x77>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| i2c@1 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x1>; |
| |
| sgtl5000: audio-codec@a { |
| #sound-dai-cells = <0>; |
| compatible = "fsl,sgtl5000"; |
| reg = <0xa>; |
| VDDA-supply = <®_1p8v>; |
| VDDIO-supply = <®_1p8v>; |
| clocks = <&sys_mclk>; |
| sclk-strength = <3>; |
| }; |
| }; |
| |
| i2c@2 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x02>; |
| |
| current-monitor@40 { |
| compatible = "ti,ina220"; |
| reg = <0x40>; |
| shunt-resistor = <500>; |
| }; |
| }; |
| |
| i2c@3 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x3>; |
| |
| temperature-sensor@4c { |
| compatible = "nxp,sa56004"; |
| reg = <0x4c>; |
| vcc-supply = <&sb_3v3>; |
| }; |
| |
| rtc@51 { |
| compatible = "nxp,pcf2129"; |
| reg = <0x51>; |
| }; |
| }; |
| }; |
| }; |
| |
| &mscc_felix { |
| status = "okay"; |
| }; |
| |
| &mscc_felix_port0 { |
| label = "swp0"; |
| managed = "in-band-status"; |
| phy-handle = <&qsgmii_phy0>; |
| phy-mode = "qsgmii"; |
| status = "okay"; |
| }; |
| |
| &mscc_felix_port1 { |
| label = "swp1"; |
| managed = "in-band-status"; |
| phy-handle = <&qsgmii_phy1>; |
| phy-mode = "qsgmii"; |
| status = "okay"; |
| }; |
| |
| &mscc_felix_port2 { |
| label = "swp2"; |
| managed = "in-band-status"; |
| phy-handle = <&qsgmii_phy2>; |
| phy-mode = "qsgmii"; |
| status = "okay"; |
| }; |
| |
| &mscc_felix_port3 { |
| label = "swp3"; |
| managed = "in-band-status"; |
| phy-handle = <&qsgmii_phy3>; |
| phy-mode = "qsgmii"; |
| status = "okay"; |
| }; |
| |
| &mscc_felix_port4 { |
| ethernet = <&enetc_port2>; |
| status = "okay"; |
| }; |
| |
| &optee { |
| status = "okay"; |
| }; |
| |
| &sai4 { |
| status = "okay"; |
| }; |
| |
| &sata { |
| status = "okay"; |
| }; |
| |
| &usb0 { |
| status = "okay"; |
| }; |
| |
| &usb1 { |
| dr_mode = "otg"; |
| status = "okay"; |
| }; |