board/wandboard/spl.c - platform/external/u-boot - Gitiles

 /*
  * Copyright (C) 2014 Wandboard
  * Author: Tungyi Lin <tungyilin1127@gmail.com>
  *         Richard Hu <hakahu@gmail.com>
  * SPDX-License-Identifier:     GPL-2.0+
  */

 #include <asm/arch/clock.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/iomux.h>
 #include <asm/arch/mx6-pins.h>
 #include <linux/errno.h>
 #include <asm/gpio.h>
 #include <asm/imx-common/iomux-v3.h>
 #include <asm/imx-common/video.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/io.h>
 #include <asm/arch/sys_proto.h>
 #include <spl.h>

 DECLARE_GLOBAL_DATA_PTR;

 #if defined(CONFIG_SPL_BUILD)
 #include <asm/arch/mx6-ddr.h>
 /*
  * Driving strength:
  *   0x30 == 40 Ohm
  *   0x28 == 48 Ohm
  */

 #define IMX6DQ_DRIVE_STRENGTH		0x30
 #define IMX6SDL_DRIVE_STRENGTH		0x28

 /* configure MX6Q/DUAL mmdc DDR io registers */
 static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
 	.dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
 	.dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
 	.dram_cas = IMX6DQ_DRIVE_STRENGTH,
 	.dram_ras = IMX6DQ_DRIVE_STRENGTH,
 	.dram_reset = IMX6DQ_DRIVE_STRENGTH,
 	.dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH,
 	.dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH,
 	.dram_sdba2 = 0x00000000,
 	.dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
 	.dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
 	.dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
 	.dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
 	.dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
 	.dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
 	.dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
 	.dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
 	.dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
 	.dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
 	.dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
 	.dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
 	.dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
 	.dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
 	.dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
 	.dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
 	.dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
 	.dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
 };

 /* configure MX6Q/DUAL mmdc GRP io registers */
 static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
 	.grp_ddr_type = 0x000c0000,
 	.grp_ddrmode_ctl = 0x00020000,
 	.grp_ddrpke = 0x00000000,
 	.grp_addds = IMX6DQ_DRIVE_STRENGTH,
 	.grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
 	.grp_ddrmode = 0x00020000,
 	.grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
 	.grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
 	.grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
 	.grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
 	.grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
 	.grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
 	.grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
 	.grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
 };

 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
 	.dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
 	.dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
 	.dram_cas = IMX6SDL_DRIVE_STRENGTH,
 	.dram_ras = IMX6SDL_DRIVE_STRENGTH,
 	.dram_reset = IMX6SDL_DRIVE_STRENGTH,
 	.dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
 	.dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
 	.dram_sdba2 = 0x00000000,
 	.dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
 	.dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
 	.dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
 	.dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
 	.dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
 	.dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
 	.dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
 	.dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
 	.dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
 	.dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
 	.dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
 	.dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
 	.dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
 	.dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
 	.dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
 	.dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
 	.dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
 	.dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
 };

 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
 	.grp_ddr_type = 0x000c0000,
 	.grp_ddrmode_ctl = 0x00020000,
 	.grp_ddrpke = 0x00000000,
 	.grp_addds = IMX6SDL_DRIVE_STRENGTH,
 	.grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
 	.grp_ddrmode = 0x00020000,
 	.grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
 	.grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
 	.grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
 	.grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
 	.grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
 	.grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
 	.grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
 	.grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
 };

 /* H5T04G63AFR-PB */
 static struct mx6_ddr3_cfg h5t04g63afr = {
 	.mem_speed = 1600,
 	.density = 4,
 	.width = 16,
 	.banks = 8,
 	.rowaddr = 15,
 	.coladdr = 10,
 	.pagesz = 2,
 	.trcd = 1375,
 	.trcmin = 4875,
 	.trasmin = 3500,
 };

 /* H5TQ2G63DFR-H9 */
 static struct mx6_ddr3_cfg h5tq2g63dfr = {
 	.mem_speed = 1333,
 	.density = 2,
 	.width = 16,
 	.banks = 8,
 	.rowaddr = 14,
 	.coladdr = 10,
 	.pagesz = 2,
 	.trcd = 1350,
 	.trcmin = 4950,
 	.trasmin = 3600,
 };

 static struct mx6_mmdc_calibration mx6q_2g_mmdc_calib = {
 	.p0_mpwldectrl0 = 0x001f001f,
 	.p0_mpwldectrl1 = 0x001f001f,
 	.p1_mpwldectrl0 = 0x001f001f,
 	.p1_mpwldectrl1 = 0x001f001f,
 	.p0_mpdgctrl0 = 0x4301030d,
 	.p0_mpdgctrl1 = 0x03020277,
 	.p1_mpdgctrl0 = 0x4300030a,
 	.p1_mpdgctrl1 = 0x02780248,
 	.p0_mprddlctl = 0x4536393b,
 	.p1_mprddlctl = 0x36353441,
 	.p0_mpwrdlctl = 0x41414743,
 	.p1_mpwrdlctl = 0x462f453f,
 };

 /* DDR 64bit 2GB */
 static struct mx6_ddr_sysinfo mem_q = {
 	.dsize		= 2,
 	.cs1_mirror	= 0,
 	/* config for full 4GB range so that get_mem_size() works */
 	.cs_density	= 32,
 	.ncs		= 1,
 	.bi_on		= 1,
 	.rtt_nom	= 1,
 	.rtt_wr		= 0,
 	.ralat		= 5,
 	.walat		= 0,
 	.mif3_mode	= 3,
 	.rst_to_cke	= 0x23,
 	.sde_to_rst	= 0x10,
 	.refsel = 1,	/* Refresh cycles at 32KHz */
 	.refr = 3,	/* 4 refresh commands per refresh cycle */
 };

 static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {
 	.p0_mpwldectrl0 = 0x001f001f,
 	.p0_mpwldectrl1 = 0x001f001f,
 	.p1_mpwldectrl0 = 0x001f001f,
 	.p1_mpwldectrl1 = 0x001f001f,
 	.p0_mpdgctrl0 = 0x420e020e,
 	.p0_mpdgctrl1 = 0x02000200,
 	.p1_mpdgctrl0 = 0x42020202,
 	.p1_mpdgctrl1 = 0x01720172,
 	.p0_mprddlctl = 0x494c4f4c,
 	.p1_mprddlctl = 0x4a4c4c49,
 	.p0_mpwrdlctl = 0x3f3f3133,
 	.p1_mpwrdlctl = 0x39373f2e,
 };

 static struct mx6_mmdc_calibration mx6s_512m_mmdc_calib = {
 	.p0_mpwldectrl0 = 0x0040003c,
 	.p0_mpwldectrl1 = 0x0032003e,
 	.p0_mpdgctrl0 = 0x42350231,
 	.p0_mpdgctrl1 = 0x021a0218,
 	.p0_mprddlctl = 0x4b4b4e49,
 	.p0_mpwrdlctl = 0x3f3f3035,
 };

 /* DDR 64bit 1GB */
 static struct mx6_ddr_sysinfo mem_dl = {
 	.dsize		= 2,
 	.cs1_mirror	= 0,
 	/* config for full 4GB range so that get_mem_size() works */
 	.cs_density	= 32,
 	.ncs		= 1,
 	.bi_on		= 1,
 	.rtt_nom	= 1,
 	.rtt_wr		= 0,
 	.ralat		= 5,
 	.walat		= 0,
 	.mif3_mode	= 3,
 	.rst_to_cke	= 0x23,
 	.sde_to_rst	= 0x10,
 	.refsel = 1,	/* Refresh cycles at 32KHz */
 	.refr = 3,	/* 4 refresh commands per refresh cycle */
 };

 /* DDR 32bit 512MB */
 static struct mx6_ddr_sysinfo mem_s = {
 	.dsize		= 1,
 	.cs1_mirror	= 0,
 	/* config for full 4GB range so that get_mem_size() works */
 	.cs_density	= 32,
 	.ncs		= 1,
 	.bi_on		= 1,
 	.rtt_nom	= 1,
 	.rtt_wr		= 0,
 	.ralat		= 5,
 	.walat		= 0,
 	.mif3_mode	= 3,
 	.rst_to_cke	= 0x23,
 	.sde_to_rst	= 0x10,
 	.refsel = 1,	/* Refresh cycles at 32KHz */
 	.refr = 3,	/* 4 refresh commands per refresh cycle */
 };

 static void ccgr_init(void)
 {
 	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;

 	writel(0x00C03F3F, &ccm->CCGR0);
 	writel(0x0030FC03, &ccm->CCGR1);
 	writel(0x0FFFC000, &ccm->CCGR2);
 	writel(0x3FF00000, &ccm->CCGR3);
 	writel(0x00FFF300, &ccm->CCGR4);
 	writel(0x0F0000C3, &ccm->CCGR5);
 	writel(0x000003FF, &ccm->CCGR6);
 }

 static void gpr_init(void)
 {
 	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;

 	/* enable AXI cache for VDOA/VPU/IPU */
 	writel(0xF00000CF, &iomux->gpr[4]);
 	/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
 	writel(0x007F007F, &iomux->gpr[6]);
 	writel(0x007F007F, &iomux->gpr[7]);
 }

 static void spl_dram_init(void)
 {
 	if (is_cpu_type(MXC_CPU_MX6SOLO)) {
 		mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
 		mx6_dram_cfg(&mem_s, &mx6s_512m_mmdc_calib, &h5tq2g63dfr);
 	} else if (is_cpu_type(MXC_CPU_MX6DL)) {
 		mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
 		mx6_dram_cfg(&mem_dl, &mx6dl_1g_mmdc_calib, &h5tq2g63dfr);
 	} else if (is_cpu_type(MXC_CPU_MX6Q)) {
 		mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
 		mx6_dram_cfg(&mem_q, &mx6q_2g_mmdc_calib, &h5t04g63afr);
 	}

 	udelay(100);
 }

 void board_init_f(ulong dummy)
 {
 	ccgr_init();

 	/* setup AIPS and disable watchdog */
 	arch_cpu_init();

 	gpr_init();

 	/* iomux */
 	board_early_init_f();

 	/* setup GP timer */
 	timer_init();

 	/* UART clocks enabled and gd valid - init serial console */
 	preloader_console_init();

 	/* DDR initialization */
 	spl_dram_init();

 	/* Clear the BSS. */
 	memset(__bss_start, 0, __bss_end - __bss_start);

 	/* load/boot image from boot device */
 	board_init_r(NULL, 0);
 }
 #endif
	/*
	* Copyright (C) 2014 Wandboard
	* Author: Tungyi Lin <tungyilin1127@gmail.com>
	* Richard Hu <hakahu@gmail.com>
	* SPDX-License-Identifier: GPL-2.0+
	*/

	#include <asm/arch/clock.h>
	#include <asm/arch/imx-regs.h>
	#include <asm/arch/iomux.h>
	#include <asm/arch/mx6-pins.h>
	#include <linux/errno.h>
	#include <asm/gpio.h>
	#include <asm/imx-common/iomux-v3.h>
	#include <asm/imx-common/video.h>
	#include <mmc.h>
	#include <fsl_esdhc.h>
	#include <asm/arch/crm_regs.h>
	#include <asm/io.h>
	#include <asm/arch/sys_proto.h>
	#include <spl.h>

	DECLARE_GLOBAL_DATA_PTR;

	#if defined(CONFIG_SPL_BUILD)
	#include <asm/arch/mx6-ddr.h>
	/*
	* Driving strength:
	* 0x30 == 40 Ohm
	* 0x28 == 48 Ohm
	*/

	#define IMX6DQ_DRIVE_STRENGTH 0x30
	#define IMX6SDL_DRIVE_STRENGTH 0x28

	/* configure MX6Q/DUAL mmdc DDR io registers */
	static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
	.dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
	.dram_cas = IMX6DQ_DRIVE_STRENGTH,
	.dram_ras = IMX6DQ_DRIVE_STRENGTH,
	.dram_reset = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdba2 = 0x00000000,
	.dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
	.dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
	.dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
	.dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
	.dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
	.dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
	.dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
	.dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
	.dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
	.dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
	};

	/* configure MX6Q/DUAL mmdc GRP io registers */
	static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
	.grp_ddr_type = 0x000c0000,
	.grp_ddrmode_ctl = 0x00020000,
	.grp_ddrpke = 0x00000000,
	.grp_addds = IMX6DQ_DRIVE_STRENGTH,
	.grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
	.grp_ddrmode = 0x00020000,
	.grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
	.grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
	.grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
	.grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
	.grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
	.grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
	.grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
	.grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
	};

	/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
	struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
	.dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
	.dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
	.dram_cas = IMX6SDL_DRIVE_STRENGTH,
	.dram_ras = IMX6SDL_DRIVE_STRENGTH,
	.dram_reset = IMX6SDL_DRIVE_STRENGTH,
	.dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
	.dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
	.dram_sdba2 = 0x00000000,
	.dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
	.dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
	.dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
	.dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
	.dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
	.dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
	.dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
	.dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
	.dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
	.dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
	.dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
	.dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
	.dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
	.dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
	.dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
	.dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
	.dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
	.dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
	};

	/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
	struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
	.grp_ddr_type = 0x000c0000,
	.grp_ddrmode_ctl = 0x00020000,
	.grp_ddrpke = 0x00000000,
	.grp_addds = IMX6SDL_DRIVE_STRENGTH,
	.grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
	.grp_ddrmode = 0x00020000,
	.grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
	.grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
	.grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
	.grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
	.grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
	.grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
	.grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
	.grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
	};

	/* H5T04G63AFR-PB */
	static struct mx6_ddr3_cfg h5t04g63afr = {
	.mem_speed = 1600,
	.density = 4,
	.width = 16,
	.banks = 8,
	.rowaddr = 15,
	.coladdr = 10,
	.pagesz = 2,
	.trcd = 1375,
	.trcmin = 4875,
	.trasmin = 3500,
	};

	/* H5TQ2G63DFR-H9 */
	static struct mx6_ddr3_cfg h5tq2g63dfr = {
	.mem_speed = 1333,
	.density = 2,
	.width = 16,
	.banks = 8,
	.rowaddr = 14,
	.coladdr = 10,
	.pagesz = 2,
	.trcd = 1350,
	.trcmin = 4950,
	.trasmin = 3600,
	};

	static struct mx6_mmdc_calibration mx6q_2g_mmdc_calib = {
	.p0_mpwldectrl0 = 0x001f001f,
	.p0_mpwldectrl1 = 0x001f001f,
	.p1_mpwldectrl0 = 0x001f001f,
	.p1_mpwldectrl1 = 0x001f001f,
	.p0_mpdgctrl0 = 0x4301030d,
	.p0_mpdgctrl1 = 0x03020277,
	.p1_mpdgctrl0 = 0x4300030a,
	.p1_mpdgctrl1 = 0x02780248,
	.p0_mprddlctl = 0x4536393b,
	.p1_mprddlctl = 0x36353441,
	.p0_mpwrdlctl = 0x41414743,
	.p1_mpwrdlctl = 0x462f453f,
	};

	/* DDR 64bit 2GB */
	static struct mx6_ddr_sysinfo mem_q = {
	.dsize = 2,
	.cs1_mirror = 0,
	/* config for full 4GB range so that get_mem_size() works */
	.cs_density = 32,
	.ncs = 1,
	.bi_on = 1,
	.rtt_nom = 1,
	.rtt_wr = 0,
	.ralat = 5,
	.walat = 0,
	.mif3_mode = 3,
	.rst_to_cke = 0x23,
	.sde_to_rst = 0x10,
	.refsel = 1, /* Refresh cycles at 32KHz */
	.refr = 3, /* 4 refresh commands per refresh cycle */
	};

	static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {
	.p0_mpwldectrl0 = 0x001f001f,
	.p0_mpwldectrl1 = 0x001f001f,
	.p1_mpwldectrl0 = 0x001f001f,
	.p1_mpwldectrl1 = 0x001f001f,
	.p0_mpdgctrl0 = 0x420e020e,
	.p0_mpdgctrl1 = 0x02000200,
	.p1_mpdgctrl0 = 0x42020202,
	.p1_mpdgctrl1 = 0x01720172,
	.p0_mprddlctl = 0x494c4f4c,
	.p1_mprddlctl = 0x4a4c4c49,
	.p0_mpwrdlctl = 0x3f3f3133,
	.p1_mpwrdlctl = 0x39373f2e,
	};

	static struct mx6_mmdc_calibration mx6s_512m_mmdc_calib = {
	.p0_mpwldectrl0 = 0x0040003c,
	.p0_mpwldectrl1 = 0x0032003e,
	.p0_mpdgctrl0 = 0x42350231,
	.p0_mpdgctrl1 = 0x021a0218,
	.p0_mprddlctl = 0x4b4b4e49,
	.p0_mpwrdlctl = 0x3f3f3035,
	};

	/* DDR 64bit 1GB */
	static struct mx6_ddr_sysinfo mem_dl = {
	.dsize = 2,
	.cs1_mirror = 0,
	/* config for full 4GB range so that get_mem_size() works */
	.cs_density = 32,
	.ncs = 1,
	.bi_on = 1,
	.rtt_nom = 1,
	.rtt_wr = 0,
	.ralat = 5,
	.walat = 0,
	.mif3_mode = 3,
	.rst_to_cke = 0x23,
	.sde_to_rst = 0x10,
	.refsel = 1, /* Refresh cycles at 32KHz */
	.refr = 3, /* 4 refresh commands per refresh cycle */
	};

	/* DDR 32bit 512MB */
	static struct mx6_ddr_sysinfo mem_s = {
	.dsize = 1,
	.cs1_mirror = 0,
	/* config for full 4GB range so that get_mem_size() works */
	.cs_density = 32,
	.ncs = 1,
	.bi_on = 1,
	.rtt_nom = 1,
	.rtt_wr = 0,
	.ralat = 5,
	.walat = 0,
	.mif3_mode = 3,
	.rst_to_cke = 0x23,
	.sde_to_rst = 0x10,
	.refsel = 1, /* Refresh cycles at 32KHz */
	.refr = 3, /* 4 refresh commands per refresh cycle */
	};

	static void ccgr_init(void)
	{
	struct mxc_ccm_reg ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;

	writel(0x00C03F3F, &ccm->CCGR0);
	writel(0x0030FC03, &ccm->CCGR1);
	writel(0x0FFFC000, &ccm->CCGR2);
	writel(0x3FF00000, &ccm->CCGR3);
	writel(0x00FFF300, &ccm->CCGR4);
	writel(0x0F0000C3, &ccm->CCGR5);
	writel(0x000003FF, &ccm->CCGR6);
	}

	static void gpr_init(void)
	{
	struct iomuxc iomux = (struct iomuxc )IOMUXC_BASE_ADDR;

	/* enable AXI cache for VDOA/VPU/IPU */
	writel(0xF00000CF, &iomux->gpr[4]);
	/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
	writel(0x007F007F, &iomux->gpr[6]);
	writel(0x007F007F, &iomux->gpr[7]);
	}

	static void spl_dram_init(void)
	{
	if (is_cpu_type(MXC_CPU_MX6SOLO)) {
	mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
	mx6_dram_cfg(&mem_s, &mx6s_512m_mmdc_calib, &h5tq2g63dfr);
	} else if (is_cpu_type(MXC_CPU_MX6DL)) {
	mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
	mx6_dram_cfg(&mem_dl, &mx6dl_1g_mmdc_calib, &h5tq2g63dfr);
	} else if (is_cpu_type(MXC_CPU_MX6Q)) {
	mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
	mx6_dram_cfg(&mem_q, &mx6q_2g_mmdc_calib, &h5t04g63afr);
	}

	udelay(100);
	}

	void board_init_f(ulong dummy)
	{
	ccgr_init();

	/* setup AIPS and disable watchdog */
	arch_cpu_init();

	gpr_init();

	/* iomux */
	board_early_init_f();

	/* setup GP timer */
	timer_init();

	/* UART clocks enabled and gd valid - init serial console */
	preloader_console_init();

	/* DDR initialization */
	spl_dram_init();

	/* Clear the BSS. */
	memset(__bss_start, 0, __bss_end - __bss_start);

	/* load/boot image from boot device */
	board_init_r(NULL, 0);
	}
	#endif